搜索资源列表
卷积码、CRC
- 卷积码的C源程序，包括编码器和译码器。 还有一个是循环荣誉校验的vhdl]源码。-convolution of C source code, including the encoder and decoder. There is a cycle of the calibration honor VHDL] source.
(2,1,3)卷积码编解码
- (2,1,3)卷积码编解码，viterbi译码
conv.rar
- 通过matlab实现对dsp的仿真 基本的离散信号处理如卷积 圆周卷积等,matlab dsp signal
DSP实验箱5502的卷积算法实验
- 这是我们学校的DSP实验箱5502的卷积算法实验,保证可以用,功能很全,它能实现对不同输入信号（正弦波、方波）的卷积结果进行比较.-This is our school s 5502 test box convolution DSP algorithm experiment, to ensure that you can use, features a very full, it can achieve for different input signal (sine wave, square
convolution_encoder_VHDL
- 卷积码编译码,由SERVICE、PSDU、TAIL和PAD域组成的DATA域应进行卷积编码，码率应根据所需的传输速率从R=1/2,2/3,3/4中选择-for 802.11a simulation WLAN FEC convolution_encoder g0=133 g1=171 Rate 0:1/2 1:2/3 2:3/4 for 802.11a simulation
juanjima
- 卷积码的生成程序,为(2,1,3)移位寄存器的卷积码生成-Convolutional code generation process for the (2,1,3) convolutional code of the shift register to generate
chengxu
- 一个分频器，一个卷积编码器的程序，都是VDHL的-A frequency divider, a convolutional encoder program, are VDHL of
viterbi
- verilog程序，实现了（2，1，4）卷积码编码，和基于回溯算法的维特比译码器-verilog program to achieve the (2,1,4) convolutional code encoding, and algorithm based on the back of the Viterbi decoder
ViterbiDecodeK9R12HardDecision
- viterbi 硬判决译码，基本实现了（2，1，9）卷积码的硬判决译码，用modelsim RTL仿真通过-hard-decision viterbi decoding, the basic realization of the (2,1,9) convolutional codes hard decision decoding, using modelsim RTL simulation through
juanjiqi
- 这是一个卷积器的设计，源码值得好好地学习-This is a convolution design, source code should be a good learning
juanji
- 实验目的：1.了解卷积算法原理。 2.掌握TMS320C5402程序的软件调试方法。 -Experimental purposes: 1. Understand the convolution algorithm. 2. TMS320C5402 procedures to master software debugging method.
115157715conv_code
- FPGA实现卷积码的功能 是一个卷积码的编译码过程实现 -FPGA realization of the function of convolutional codes
dspjuanji
- CCS 6000的DSP卷积运算的源码,可以-this is a program for DSP
conv_enc
- 这是一个用VERILOG HDL编写的卷积码程序-This is a VERILOG HDL with the preparation of procedures for the convolutional codes
Ex4_1
- 在一台装有CCS软件的计算机，用C语言编写DSP程序：卷积运算-convolve
cc_encode
- 卷积码，并行编码，FPGA，通过了测试验证-CC Code， Parallel Coding， FPGA
Convolutionalencoder
- 应用VHDL语言实现的卷积编码器的应用程序-Application of VHDL language implementation of the convolutional encoder applications
（2,1,3）卷积编码和viterbi译码
- 自己写的（2,1,3）卷积编码器和viterbi译码，测试已通过
卷积交织器解交织器设计
- 交织技术通常分为分组交织和卷积交织。分组交织过程是数据先按行写入，再按列读出；解交织过程是数据先按列写入，再按行读出。其特点是结构简单，但数据延时时间长，而且所需的存储器比较大。(Interleaving techniques are usually divided into packet interleaving and convolution interleaving. Packet interleaving process is the first data written by row,
线性卷积和圆周卷积
- 圆周卷积和线性卷积的运算 分别用了MATLAB的conv函数(Linear convolution and circumferential convolution)