verilog编写的ADS774控制程序,由于ADS774数字量输出不稳定,建议取平均值-control program written in verilog ADS774, ADS774 digital output as unstable, the proposed averaging

verilog 双模块算术平均值计算模块，子模块在时钟上升沿技术，高层模块根据当前计数值计算算数平均-verilog double module arithmetic mean calculation module, sub-module in the clock rising edge technology, high-level module is calculated based on arithmetic average of the current count

AD递推平均滤波算法，采用verilog完成，可直接使用。-AD recursive average filter algorithm, using verilog complete, can be used directly.