搜索资源列表
DIF_FFT
- 按频率抽取计算FFT的C++源代码，可以较方便地移植到有C/C++开发环境的DSP中去-by FFT frequency calculated from the C source code, can be easily ported to the C / C development environment to the DSP
cic3s32
- 一个3阶的32位抽取的cic滤波器的verilog源代码
cic
- verilog码写的CIC滤波器的程序，包括4倍抽取CIC滤波器和内插的CIC滤波器两个
CICdeVHDL
- 本人编写的3级抽取器的vhdl代码,可供大家参考一下，如有不妥之处，还请多多指教.
ImproveddesignofCICfilteranditsimplementationonFPG
- 。介绍了内插器和抽取器这2种CIC滤波器各自的结构与性能，从数学上分析了其性能及其与FIR 滤波器的关系，从频域上展示了其本质。并讨论其内部寄存器的最小位宽与溢出保护，最后介绍了抽取器与内插器分 别在FPGA上的一般实现方法，并指出了一些提高实现性能的措施与建议
DecimationFilterDesignforDDCandImplementingItwithF
- 本文介绍了在数字下变频(DDC) 中的抽取滤波器系统设计方法和具体实现方案。采用CIC 滤波器、HB 滤波器、FIR 滤波器三级级联的方式来降低采样率。通过实际验证,证明了设计的可行性
cic3s32
- 阶的32倍抽取cic滤波器verilog代码
cic_4_dec
- 实现4倍抽取的CIC抽取滤波器模块的Verilog实现，在对数据进行抽取之前，首先进行滤波
CIC_deci4.rar
- cic抽取滤波器ip核，用于射频采样数字下变频模块的核心数字信号处理部分.此ip核已经过ise10.2验证,CIC decimation by 4 filter，used in Direct RF sampling of GPS signal. the core dsp block in a frondend design
CIC_DEC
- CIC抽取滤波器设计，CIC滤波器采用5阶8倍抽取。-CIC decimation filter design, CIC filter order of 8 times 5 samples.
multiratewebinar_oct2005_english
- 多级抽取程序,适用于软件无线电系统，matlab编写，验证！希望对大家有用。-Multi-stage extraction procedure, applied to software radio systems, matlab prepared to verify! Hope useful for everyone.
fft-DIF
- 自己编写的C语言基于频率抽取的基2FFT算法，用于大家学习交流-I have written C language based on the frequency of taking the base 2FFT algorithm, for them to learn from the exchange of
fft-DIT
- C语言编写的基于时间抽取的基2FFT算法-C language based on the time taken to prepare the base 2FFT algorithm
FFT
- 基于dsp的fft算法，是基2按时间抽取快速fft，对于想熟悉fft算法的朋友很有帮助-Based on the dsp of the fft algorithm, is extracted by time radix-2 fast fft, for want of a friend familiar with the fft algorithm helpful
CIC4_fir_comp_mlab
- CIC抽取补偿滤波器设计，CIC滤波器采用5阶4倍抽取。-CIC compensation filter design samples, CIC filter order 4 times using 5 samples.
CIC_DEC_4
- CIC抽取滤波器设计，CIC滤波器采用5阶4倍抽取。-CIC decimation filter design, CIC filter order 4 times using 5 samples.
CIC_DEC_6
- CIC抽取滤波器设计，CIC滤波器采用5阶6倍抽取。-CIC decimation filter design, CIC filter stage 6 times 5 samples.
verilog
- 本代码设计的是一个通讯系统软件无线电中变换比为5/4的分数倍抽取器，用Verilog编程首先实现4倍内插，再实现5倍抽取。-The code design is a software-defined radio communication system in transformation ratio 5/4 points times the extractor, using Verilog programming the first to achieve four times the inter
cic_dec_8_five
- CIC抽取滤波器，抽取系数8,verilog版本，用于数字下变频-CIC decimation filter, extraction coefficient of 8, verilog version, for digital down-conversion
DDC中的抽取滤波器设计及FPGA实现
- 本文对下变频模块中抽取滤波进行了详细的分析，并详细阐述了其FPGA的实现过程和方法(In this paper, the decimation filtering in the down conversion module is analyzed in detail, and the realization process and method of FPGA are discussed in detail)