搜索资源列表
PN-arraycheck
- 在QuartusII运用ＡＨＤＬ语言，首先设计出PN发生器来产生一个11位的数据流在整个周期内有效数据有 =2047位；再设计状态机用来检测串行数据流中的序列。运用两个个计数器分别对PN码计数以及序列出现的次数计数。改变ＰＮ码结构可以作为通用数列检测器
simple_app
- TMS320c672x通过DSPLIB库实现复数FFT，并可实现两个实数数列的高效FFT。-TMS320c672x achieved through DSPLIB library complex FFT, and can realize two real sequences efficient FFT.
fib_shulie
- 能够产生雯波契那数列，并在LED数码管上显示-Wenbo Qi series that can generate and display in the LED digital tube
DSP_Cal
- VB编写的程序关于DSP28335计算数列的程序-Programs written in VB calculation on the DSP28335 series of procedures
Find_The_Prime
- VHDL 代码，用于查找一个数列的素数搜寻器。-Prime Number comparator
shujupaixu
- 自行在片内RAM30H-3FH单元中给出一组随机数，将数据块排序，使之从大到小成为有序数列-On their own in-chip RAM30H-3FH unit is given a set of random numbers, sorting the data block, so that the number of columns in descending order as
Fibonacci
- Fibonacci数列的VHDL实现，程序细分为了各个模块实现了Fibonacci数列计算。Fibonacci数列：1,1,2,3，5，8...即当前元素为前两个元素之和。-Fibonacci sequence of VHDL, the program modules in order to achieve sub-Fibonacci series. Fibonacci numbers: 1,1,2,3,5,8 ... that is the current element and the fi
cal_fun
- 采用简单的线性内插方式，实现在有序数列中查找对应点，常用于外部AD采集获得的数据列表查询，提高精度，本程序提供良好的函数接口和一些基本函数供用户使用。-Using simple linear interpolation, and find the corresponding points in the sequential number column, to obtain a list of data on external AD acquisition commonly used query,
ISE_lab10_fib
- excd-1 斐波那契数列的实现 数码管的显示-excd-1 fib
LCD-Picture-transformer
- 适用于CORTEX M3芯片刷屏的图片转换程序，能将大小为240*360 的图片转换成相应的点阵数列（适用于神州系列的开发板）-The CORTEX M3 chip scraper suitable for image conversion program, can the size of 240* 360 images into corresponding lattice series
fib
- 一个基于VHDL编程的可用于FPGA实现的斐波那契数列计算器- implemented a circuit in VHDL that calculates Fibonacci numbers
斐波那契数列Verilog实现
- 斐波那契数列Verilog实现
feibonaqi
- 斐波那契数列，用VErilog语言实现非常好-Fibonacci sequence, using VErilog language is very good ha ha ha ha ha ha ha
random
- STC89C52单片机上已成功实现，利用计数器产生伪随机数列，基本可以满足要求-STC89C52 single-chip has been successfully achieved, the use of counter generates a pseudo-random sequence, to meet the basic requirements
MyFFT
- 基于C语言的任意n点FFT算法实现。可自动实现16位以内的位倒序。输入实数数列，输出复数数列。-The realization of arbitrary point n C language based on FFT algorithm. Bit reverse more than 16 can automatically realize. In real sequence, the output of complex numbers.
RAM
- 用verilog实现了IP核的使用，例化了一个RAM，用来进行读写操作，另外还编写了斐波那契数列来进行测试。-Using verilog to achieve the use of IP core, the instantiation of a RAM, used to read and write operations, in addition to the preparation of the Fibonacci sequence for testing.
Fibonacci
- （1） clkdiv 模块：对50MHz 系统时钟 进行分频，分别得到190Hz，3Hz 信号。190Hz 信号用于动态扫描模块位选信号，3Hz 信号用于fib 模块。 （2） fib 模块：依据实验原理所述Fibonacci 数列原理，用VHDL 语言实现数列 （3） binbcd14：实现二进制码到BCD 码的转换，用于数码管显示。 （4） x7segbc：采用动态扫描，使用4 位数码管依次显示Fibonacci 数列数据。 实验采用3Hz 频率来产生Fibonacci
C6713-TIME-FFT
- 基于DSP6713处理器开发的FFT函数程序包，实现数列的FFT变换-DSP6713 processor based on the development of FFT function package, to achieve the sequence of FFT transform