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pwm
- pwm的占空比和死区时间可调的Verilog HDL程序设计和测试-duty cycle of pwm and adjustable dead time of the Verilog HDL design and testing procedures
Tri_SPWM
- 带有3次谐波注入的SPWM波的实现，基于2812的环境，带有死区时间，调制比0.8,N=123-With 3rd harmonic injection SPWM wave realization 2812-based environment with dead time, modulation ratio 0.8, N = 123
spwm
- 用2812的时间管理器，产生不带死区的6路互补的SPWM，通过在2812上已调试成功-The time manager with 2812, resulting in a dead zone 6 with no way complementary SPWM, passed in 2812 has been successful commissioning
spwm3
- 通过0，1序列来产生所需SPWM信号，带死区时间。可通过该SPWM信号通过H桥式电路控制电流形状。-The time required to generate SPWM signals with dead by 0,1 sequence. By H-bridge circuit to control the current through the SPWM signal shape.