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ADC0809control
- 状态机对ADC0809的采样控制电路程序-State machine control circuit of the ADC0809 sampling procedures
fsm_keyboard
- 使用状态机的通用键盘程序（支持组合键），可以作为状态机编程的一个示例 -The use of state machine Universal Keyboard program (to support combination of keys), can be used as an example of state machine programming
calculator
- 自己写的计算器，基于c51单片机写的，用protues完美模拟，原理是有限状态机，呵呵，含有三个版本，能完成基本的四则运算，键盘流出空闲，方便后来者扩展-Write your own calculator, based on c51 microcontroller written by protues perfect simulation, the principle is a finite state machine, Oh, containing three versions, to com
key
- 基于雨亭的51/AVR单片机开发板的按键扫描程序，在定时器中断中定时扫描，使用状态机进行按键去抖，与延时扫描相比效率较高，占用资源少-Yu Ting s 51/AVR microcontroller based development board scanner button, the timer interrupt in time scan, using the state machine button to shake, as compared with the delayed scan m
FSM
- 有限状态机设计指导,详细介绍了设计状态机过程中的有关经验，以及各种状态机设计的相互优劣对比-Finite state machine design guidance, details of the design state machine during the relevant experience, as well as various advantages and disadvantages of each state machine design comparison
LCD_SCREEN
- 利用了状态机的53种状态太分别描述LCD显示频的初始化、显示字符串“OK!”的时序图中的详细过程-Use of 53 states of state machine LCD display is too describe the frequency initialized, the string " OK!" The timing diagram of the detailed process
state
- verilog语言编写的高效状态机设计，值得好好学习一下-verilog language efficient state machine design, it is well to study the
Three-stage-state-machine
- 状态机是逻辑设计的重要内容，状态机的设计水平直接反应工程师的逻辑功底，所以许 多公司的硬件和逻辑工程师面试中，状态机设计几乎是必选题目。本章在引入状态机设计思想的基础上，重点讨论如何写好状态机。-State machine is an important part of logic design, state machine design engineers a direct response to the logic level of skills, so the company s ha
zhuantaiji
- 简单的状态机设计，功能是检测一个5位二进制序列“10010”。考虑到序列重叠的可能，有限状态机共提供8个状态（包括初始状态IDLE）。-Simple state machine design, function is to detect a 5-bit binary sequence " 10010." Taking into account the possibility of overlapping sequences, finite state machines prov
statemachine
- 使用有限状态机的概念实现小型仪器多机通信协议，具有很高的稳定性与可靠性。-The concept of finite state machines using a small instrument to achieve multi-machine communication protocol, with high stability and reliability.
Verilog
- 用verilog实现七位最大公约数的算法，使用状态机，可仿真电路图-Seven with the greatest common divisor algorithm verilog implementation, the use of state machine circuit simulation
USE_FSM_DEDIGN_SRAM
- 用FSM（有限状态机）设计SRAM的VHDL语言-With the FSM (finite state machine) design of the VHDL language SRAM
dct01
- Verilog编写的串口通讯下解码状态机-Verilog serial communication prepared under the decoder state machine
Verilog-HDL
- 这是关于VERILOG HDL的有限状态机的源码，大家参考参考，应该有好处的。-This is about VERILOG HDL source code for finite state machines, we refer to the reference, it should be good.
FSM
- 文章介绍的状态机的优化写法，并给出经典实例。使读者更清楚的明了FPGA中状态机的优点，以便工程中的使用。-This paper introduces the optimization of state machines written, and gives the classic example. So that readers understand more clearly the advantages of FPGA in the state machine to the project u
dir3
- VERILOG 语言写的使用状态机实现奇数分频-VERILOG language is written by the state machine to implement an odd number of points frequency
Time_Triggered_system
- 基于51单片机的状态机的多任务处理教你如何写程序很实用 -51 single-chip state machine based multi-tasking to teach you how to write useful programs
State-machine-clock
- 状态机思想写的51单片机驱动的时钟，含ROTEUS仿真文件-Idea to write state machine 51 microcontroller-driven clock, simulation files containing ROTEUS
LQB G7
- 蓝桥杯第七届国赛代码（状态机扫描矩阵键盘、中断数码管显示、软件IIC、片内EEPROM、带DS18B20\DS1302）(Blue Bridge Cup seventh Tournament (state machine code scan matrix keyboard interrupt, digital display, IIC software, EEPROM, chip with DS18B20\DS1302))
jtag fsm
- jtag接口的状态机实现，李庆华《通信IC设计》随机代码(State machine implementation of JTAG interface)