搜索资源列表
RISC-CPU
- 用FPGA实现一个简易的CPU,采用精简指令集结构,每一条指令有16bit,高三位为指令操作数,后13位为地址,该CPU能实现8种指令操作,分别有HLT(空一个中期)ADD(相加操作)SKZ(为零跳过)AND(相与操作)XOR(异或操作)LDA(读数据)STO(写数据)JMP(无条件跳转指令)。cpu包括8个部件,分别为时钟发生器、指令寄存器、累加器、算术逻辑单元、数据控制器、状态控制器、程序计数器、地址多路器,各个部件之间的相互操作关系由状态控制器来控制,程序指令存放在初始rom中,本例程存放
sum_ten
- 十位累加器,EDA,FPGA,DDS信号发生器的相位累加器,可用.-Accumulator 10, EDA, FPGA, DDS signal generator of the phase accumulator can be used.
acc
- 自己使用AHDL语言编写的24位累加器.主要使用于DDS-24bit_acc
division
- 分别用分频比交错法及累加器分频法完成非整数分频器设计。-Points were staggered method and frequency than the frequency accumulator law to complete the design of non-integer divider.
FPGA_DDS
- 本文介绍了如何用VHDL进行DDS的设计,其中关键的相位累加器,正弦信号发生器等用VHDL描述-the DDS is depend on the fpga ,and we descr iption it use the vhdl
myproject
- dsp的实验累加器编写的程序 实现累加功能 比较简单-dsp experimental procedure for the preparation of accumulator function is relatively simple to achieve cumulative
65jie
- 串并FIR滤波器设计:并行FIR滤波器具有速度快、容易设计的特点,但是要占用大量的资源。在多阶数的亚高频系统设计中,使用并行结构并不合算,但亚高频系统需要较高的处理速度,而串行架构往往达不到要求,因此,结合串并这两种设计方法的长处,在使用较少的硬件资源的同时实现了较高的处理速度,这里说明一种65阶八路并行、支路串行FIR滤波器的设计(实际使用了1个乘法器,8个乘累加器,一个累加器)。-String and FIR filter design: parallel FIR filter with a
C10_PulseAccumulate
- 脉冲累加器的使用程序,希望对大家有点帮助-Procedures for the use of pulse accumulator, I hope all of you a little help
PulseAccumulate
- 这是MC9S12DG128定时器模块中脉冲累加器应用实例-This is MC9S12DG128 timer pulse accumulator module Applications
xunzhi
- DSP C5400的数据寻址汇编程序,含各种数据寻址方式,包括立即寻址,绝对寻址,累加器寻址,直接寻址,间接寻址,存储器映像寄存器寻址和堆栈寻址-DSP C5400 data addressing assembler, containing a variety of data addressing modes, including an immediate addressing, absolute addressing, accumulator addressing, direct addres
83390078DDS
- DDS的工作原理是以数控振荡器的方式产生频率、相位可控制的正弦波。电路一般包括基准时钟、频率累加器、相位累加器、幅度/相位转换电路、D/A转换器和低通滤波器(LPF)。频率累加器对输入信号进行累加运算,产生频率控制数据X(frequency data或相位步进量)。相位累加器由N位全加器和N位累加寄存器级联而成,对代表频率的2进制码进行累加运算,是典型的反馈电路,产生累加结果Y。幅度/相位转换电路实质上是一个波形寄存器,以供查表使用。读出的数据送入D/A转换器和低通滤波器。-DDS works
chap3
- 一段小小的四位累加器的实现程序,通过仿真测试,免费下载-The realization of a small four accumulator process simulation test, free download
xiangweileijiaqi
- 相位累加器,是数字频率合成器的重要组成部分。这是verilog代码。-Phase accumulator, digital frequency synthesizer is an important part. This is the verilog code.
Sources
- 基于S12单片机和hq7620摄像头的图像采集程序(脉冲累加器溢出中断采集,输入捕捉中断发送数据给PC机)-picture sampling based on S12 MCU and hq7620 using interrupt.
leijiaqi
- 16位流水线加法累加器,用VHDL语言实现,编译仿真通过。-16-bit pipelined adder accumulator, using VHDL language, compiled simulation through.
S12_frequency
- S12的脉冲累加器实现测频,模数减法器实现时间基准,精度高,12864显示。-S12 pulse accumulator for detecting frequency modulus subtraction time basis to achieve high precision, 12864 display.
S12_frequency_pulsewide
- S12多个脉冲累加器实现频率和脉宽的测量,供网友参考添加功能实现占空比的测量。-S12 pulse accumulator to achieve multiple frequency and pulse width measurement, for users to add functionality to achieve the duty cycle reference measurement.
S12_RTI_Clock
- S12实时时钟实验,S12的另一个实现时间基准的程序,可配合脉冲累加器测频等。-S12 Real-Time Clock test, S12, another realization of the program time base can be measured with the pulse frequency and accumulator.
leijiaqi
- 累加器 的VHDL语言源程序~-Accumulator accumulator VHDL language source ~
nios_dds
- 采用Altera的NIOS内核,配合独立的累加器,实现了正弦波,三角波,锯齿波和方波的DDS产生电路,系统时钟最高可达120MHz,配合高速DAC,可产生最高约40MHz左右的波形-Using Altera' s NIOS core, with a separate accumulator, to achieve a sine wave, triangle wave, sawtooth and square wave generation circuit DDS system clock