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NCO
- 基于FPGA的DDS设计，通过外接DA转换器输出稳定的正弦波，方波和三角波，可单独产生时钟，不必借助硬件连接，包含寄存器程序，累加器程序和时钟发生电路等，以及顶层设计原理图-The DDS FPGA-based design, through an external DA converter output stable sine wave, square wave and triangular wave, can produce a single clock, without the help
counter
- FPGA编程，用Verilog语言实现4位累加器功能-The FPGA programming, realize four accumulator with Verilog language features
s5
- 清华大学电子系 时序逻辑实验报告 包括：触发器设计，计数器设计，累加器设计，序列检测器设计/有限状态机实现-Tsinghua University, Department of Electronics, sequential logic test report include: trigger design, counter design, accumulator design, the sequence detector design/finite state machine
add_sin
- 使用quartus软件编写VHDL语言一个累加器程序-Quartus software using VHDL language to write a program accumulator
add1A
- 用于实现锁相光子计数技术的累加器，verilog语言-Accumulator achieve specific cases for accumulator lock detection of photon counting technique
pipeline_add
- pipeline式累加器的verilog代码和testbench文件，已验证-pipeline type accumulator verilog testbench code and documents, verified
sin_en
- DDS 由相位增量器，相位累加器，量化器以及正余弦查找表四部分组成。 相位累加器每一周期会累加上固定的相位值，然后从查找表中找到对应的数值。-DDS by the phase increment, phase accumulator, quantizer and sine and cosine lookup table of four parts. The phase accumulator accumulates a fixed phase value for each period,
TIM
- 飞思卡儿 计时器time 的脉冲累加器产生原理的例子，已经测试通过。-Freescale timer time pulse accumulator produces an example of the principle that has been tested.
eda
- 直接数字频率 相位累加器 寄存器 lpm_rom(Based on VHDL+ FPGA design of the DDS signal has been through mode)