搜索资源列表
Com_Queue
- 单片机串口接收缓存队列的简单实现,由C语言实现,性能稳定,移植方便可靠!-Microcontroller serial port to receive buffer queue to achieve a simple, achieved by the C language, stable performance, reliable and convenient transplantation!
SRAM_FPGA
- sram缓存数据,用VHDL语言编程,已经验证过!很 好用的!-SRAM cache data, using VHDL language programming, has already been verified! Very good use!
Circle
- msp430f149 实现环形缓存区功能代码-msp430f149 ring buffer function code
Sender
- 反射内存卡的发送数据程序,包括板卡的打开,以及数据从缓存区写入反射内存。-sender program of RFM
lcd_buffer
- 12864单片机内缓存显示,实现无字库显示中文,自动检索。-12864 single-chip cache to free font to display Chinese, the automatic retrieval.
fifo_module
- 基于vhdl的FIFO建模,主要是用于输入输出数据缓存-Vhdl-based FIFO modeling is mainly used for input and output data cache
FIFO
- FIFO是英文First In First Out 的缩写,是一种先进先出的数据缓存器,他与普通存 储器的区别是没有外部读写地址线,这样使用起来非常简单,但缺点就是只能顺序写 入数据,顺序的读出数据,其数据地址由内部读写指针自动加1完成,不能像普通存 储器那样可以由地址线决定读取或写入某个指定的地址-FIFO is the abbreviation of the English First In First Out, a FIFO data buffer, the differen
display
- LCD显示程序代码,很详细的程序。用于驱动LCD刷新,及数据缓存-LCD display program, a very detailed program annotations
Audio_DAC_FIFO
- 用于做多媒体缓存的源码 可以做整帧的缓存-SquiDeral- manipulating the cache usage of Your Audio.
syn_FIFO
- 同步FIFO,主要用于数据缓存,给异步FIFO打下基础,是个不错学习例子,在ncverilog中仿真通过-Synchronous FIFO, mainly used for the data cache, and lay the foundation to the asynchronous FIFO, is a good example of learning through simulation in ncverilog
UART_DMA
- 串口通信的FPGA设计,具有高速缓存功能,DMA通信模式。-FPGA design of serial communication, cache, DMA communication mode.
Virtex-5-FPGA-Data-Sheet
- 本程序基于xilinx fpga,v5,verilog语言,主要用于数据采集,采集频率可达500m,通过pingpang缓存进行数据转发。-The program xilinx fpga, v5, verilog language, mainly used for data acquisition, acquisition frequency of up to 500m, through data forwarding pingpang cache.
AT45DB081duxie
- c8051f020单片机下的at45db081读写程序,缓存1用于写数据,缓存2用于读数据。-c8051f020 microcontroller under the at45db081 of reading and writing process, cache is used to write data cache 2 is used to read data.
9.17
- 1.串口中断允许自动接收总线上的信息,当接收的字节后超过3.5个字节时间没有新的字节认为本次接收完成,接收完成标志置1 如果接收完成标志已经置1又有数据进来则丢弃新来的数据。 2.串口接收数据的处理, 当接收完成标志置1进入接收数据处理, (1)首先判断接收的第一位数据与本机地址是否相同,如果不相同清空接收缓存不发送任何信息 (2)接收的第一位数据与本机地址相同,则对接收缓存中的数据进行crc16校验,如果接收的校验位与本校验结果不相同清空接收缓存不发送任何信息;(3)如果crc16校验正
eetop.cn_emif_brg
- fpga与DSP通过emif接口通信,fpga内部通过fifo进行数据缓存-fpga with the DSP through emif interface communication, fpga internal data cache by fifo
asynchronous-FIFO-verilog
- FIFO是英文First In First Out 的缩写,是一种先进先出的数据缓存器,他与普通存储器的区别是没有外部读写地址线,这样使用起来非常简单-FIFO is an abbreviation of the English First In First Out, is a first-in, first-out data buffer, the difference between him and ordinary memory is external read and write add
chuankou
- 这个是串口通信的实验,通过中断实现,程序完整,并涉及到了缓存一些知识-This is a serial communication experiment, by interrupt achieve, the integrity of the process, and involves some knowledge of the cache
FPGA_sram_fifo
- 普通数据传输源码,采用SRAM虚拟FIFO做数据缓存。该虚拟FIFO只做外部数据上传到电脑的数据缓存。-Ordinary data transmission source, using SRAM virtual FIFO data cache. The virtual FIFO only the external data uploaded to the computer data cache.
divider_with_cache
- 带缓存的除法器,包括test bench,在普通除法器上加上缓存功能-divider with cache
RGB_Out
- BF548 EPPI应用范例。例子使用EPPI RGB888/RGB666传输模式和SHARP LQ043T1DG01 LCD驱动。程序在LCD上面输出选定的显示模式。2个RGB888缓存区用于创建显示模式。-This is an example program for EPPI RGB888/RGB666 transmit modes and SHARP LQ043T1DG01 LCD driver.The program outputs a seleted display pattern t