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VHDL-XILINX-EXAMPLE26
- [VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][6--8位并入串出寄存器][7--内部三态总线][8--含清零和同步时钟使能的4位加法计数器][9--数控分频器][10--4位十进制频率计][11--译码扫描显示电路][12--用状态机实现序列检测器的设计][13--用状态机对ADC0832电路控制实现SIN函数发生器][14--用状态机实现AD
FPGA控制AD程序,ADC,DAC转换接口
- FPGA控制AD程序,ADC,DAC转换接口.rar 有限状态机控制AD采样.rar,FPGA control AD procedure
CIC_deci4.rar
- cic抽取滤波器ip核,用于射频采样数字下变频模块的核心数字信号处理部分.此ip核已经过ise10.2验证,CIC decimation by 4 filter,used in Direct RF sampling of GPS signal. the core dsp block in a frondend design
sin.rar
- 用Verilog语言在FPGA内实现一256个采样点的正弦波,已尝试,挺好用的~~~,Verilog language used in the FPGA to achieve one of the 256 sampling points sine wave, I have already tried it, very useful~ ~ ~
TLC2543
- 使用Verilog实现的AD采样,很有用的!-Implemented using Verilog AD sampling, very useful!
ADcontroller
- FPGA控制AD7610采样.此为通用控制器模块.其中ADC16BITs串行传入FPGA后,串行数据转换成16BIT并行数据-ADC controller
TLC549
- verilog TLC549AD采样程序 ,速度200K,在LED和数码管上显-verilog TLC549AD sampling procedures, the speed of 200K, in the LED and digital tube significantly
ADC_Fre_counter_LED_keyboard
- FPGA tlc0820采样控制 高精度测频 LED键盘显示 VHDl 调试与EP1C3-FPGA vhdl ADC LED keyboard frequency counter test
TLC5510_IIPRAM1
- FPGA控制双口RAM、实现TLC5510采样控制双口RAM读写!QUARTUS II8.0平台仿真验证通过,并在硬件上运行通过测试!-FPGA control of dual-port RAM, the realization of sampled-data control TLC5510 dual-port RAM read and write! QUARTUS II8.0 platform through simulation and hardware to run through the
SPWM
- VHDL采用自然采样法写的SPWM,里面有正弦表,可以通过外接输入正弦波和三角波的频率。 -VHDL using written natural sampling SPWM, there are sine table, you can enter through the external sinusoidal and triangular wave frequency.
wavegenerator
- 开发环境为QuartusII,能产生正弦波、三角波、方波和锯齿波,幅度为5V,采样为8位,在开发板已经验证通过,有详细的波形图和管脚分配图。-Development environment for QuartusII, can generate sine wave, triangle wave, square wave and sawtooth wave, ranging from 5V, sampling for 8, in the development board has to verif
EP1C3_12_5_RSV
- 基于FPGA的数字存储示波器,用VHDL实现的,压缩包里是Quartus工程。AD采样送进FPGA,存入SRAM后用DA在普通示波器上可以显示。-FPGA-based digital storage oscilloscope, using VHDL achieved compression is Quartus project bag. AD sample into FPGA, after SRAM into DA in ordinary oscilloscope can display.
61EDA_D954
- 用FPGA实现的ADC采样器,用vhdl编写,spi总线-FPGA implementation using the ADC sampler, prepared using VHDL, spi bus
LVDS_DDR_List_FPGA2
- FPGA芯片与ADI公司的AD9779之间的通信,总共有四个通道,68对LVDS,采样时钟是122.88MHz-FPGA chips ADI' s AD9779 and communication between, a total of four channels, 68 pairs of LVDS, the sampling clock is 122.88MHz
ADC0809
- 用状态机对A/D转换器0809的采样控制电路的实现。工具:Quartus ii 6.0 语言:VHDL-State machine used for A/D converter sampling control circuit 0809 is achieved. Tools: Quartus ii 6.0 Language: VHDL
somethingaboutADC0809
- 8.4 ADC0809接口电路及程序设计 ADC0808/ADC0809资料; 基于VerilogHDL的ADC0809采样控制器设计; 基于VHDL语言的A_D采样控制器设计。 -8.4 ADC0809 interface circuit and program design ADC0808/ADC0809 information ADC0809 based on the sampling VerilogHDL controller design A_D languag
lpf
- 实现低通采样功能的vhdl代码,可在quartus里运行。-The achievement of low-pass function vhdl sample code can be run in quartus.
shukongzhiliudianyuan
- 介绍了一种闭环智能数控直流电流源的设计原理和实施方案,该方案采用自行设计制作的高精度电压源,利用单片机、PWM和运算放大器构成A/DD/A转换器来控制场效应管导通状态的原理,达到了输出恒流的目的。整个系统采用89C58单片机作为主控部件,将预置电流值数据送入D/A转换器,经硬件电路变换为恒定的直流输出,同时使用采样电阻将实际输出电流转换成电压送入A/D转换器,并将其反馈到单片机中构成闭环系统,进而实现预设值和实际值的比较,再通过调整D /A转换器输出的电压来改变场效应管的导通状态,减小了实际值与
ad_conv
- 利用CPLD来控制AD进行电压采样,并将采样值输出-CPLD to control the use of AD to voltage sampling, and sampling the value of output
caiyang
- 种用FPGA 实现对高速A/ D 转换芯片的控制电路,系统以MAX125 为例,详细介绍了含有FIFO 存储器的A/ D 采样控制电路的设计方法,并给出了A/D 采样控制电路的V HDL 源程序和整个采样存储的顶层电路原理图.-Species with FPGA to achieve high-speed A/D conversion chip control circuit, the system as an example to MAX125 details FIFO memory cont