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数字系统设计教程4_9
- vhdl的几个编程,4位除法器的设计和原理说明,还有8位CPU设计-VHDL programming, the four division and the design principle that there are eight CPU Design
数字系统设计相关
- 这是有关VHDL的相关源代码,有简易CPU、加法器、除法器、计数器等-This is the relevance of the VHDL source code, a simple CPU, Adder, Divider, counters, etc.
VHDL5
- 加法器 乘法器电路 除法器电路设计 键盘扫描电路设计 显示电路-Adder multiplier circuit divider circuit design keyboard scan circuit design show circuit, etc.
fixed_pointDivider
- 本人编写的定点除法器,开发软件为XILINX的ISE6.2,通过PAR仿真.-I prepared for the sentinel division, the development of software for the ISE6.2 Xilinx, PAR through simulation.
VHDLchufaqi
- MAXPLUS2 自己编写的VHDL 4位除法器-MAXPLUS2 prepare themselves VHDL four Divider
verlog_basic
- 用verlog语言编的一些基础实验,适合于FPGA/CPLD的初学者。内容包括8位优先编码器,乘法器,除法器,多路选择器,二进制转BCD码,加法器,减法器等等。-verlog used some language addendum to the basic experiment, which is suitable for FPGA / CPLD beginners. Including eight priority encoder, multipliers, dividers, multi-p
DivArrUns
- 用VHDL实现的除法器,非常好使,仿真通过了
divider
- 介绍了除法器的设计,采用verilogHDL语言,利用modelsim仿真验证,压缩包中包含了流程图
div2
- 32位除法器 被除数和除数均为16位整数,16位小数 商为32位整数,16位小数 余数为16位整数,16位小数 Verilog HDL 代码
VHDL语言写的简易计算器
- 用VHDL写的简易计算器,包括加减乘除,除法器用加法器和乘法器组成-Write simple calculator with VHDL, division, including add, subtract, multiply and divide adder on time-multiplier and used
fast_divider
- 快速除法器,采用循环移位相减算法。 已经通过仿真。-Quick divider using cyclic shift subtraction algorithm. Simulation has been passed.
division1
- 基于vhdl/verilog的18位除法器程序。已经过仿真和综合。-Based on vhdl/verilog program for 18-bit divider. Has been simulation and synthesis.
div_8
- 八位除法器 VHDL实现 八位除法器 VHDL实现-8-Bit divider 8-Bit divider 8-Bit divider
div
- 二进制除法器,采用移位相减的方法实现,位数可调-The source code of a divider
divider
- 带时钟及控制的多位除法器设计,利用状态机来实现控制-multi-cycle divider design
div
- 实现了不恢复余数除法器,采用Verilog HDL编码,仿真通过。-Not to restore the balance achieved divider, using Verilog HDL coding, simulation through.
div
- VERILOG除法器,已经调试好。大家可以参照学习.-sub-divided function,I have debug it right.It is helpful to you
divider
- FPGA除法器的使用32位的,有商和余数-FPGA using 32-bit divider, there are the quotient and remainder
Dividers
- 文件中包括各种除法器,不同类型的,不同算法的。(The document includes a variety of divider, different types, different algorithms.)
devided
- 一个16位除8位的除法器,能够输出余数和商。(In addition to a 16 bit 8 bit divider, can output the remainder and quotient.by stan)