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verilog_18bit_Div
- verilog编写的18位输入高精度的除法器，带说明文件和测试代码。-18 input precision divider verilog prepared with documentation and test code.
divider
- verilog HDL编写的浮点除法器，编译通过，可综合。压缩包包含三个文件。-verilog HDL write floating-point divider, compile, can be integrated. Archive contains three files.
immediate_divide_module
- 用组合逻辑实现循环除法器。稳定、安全、可靠。-Combinational logic loop divider. Stable, secure, and reliable.
divider
- 基于Verilog的除法器设计，可以直接在Q2里面运行哦~-Verilog-based design of the divider, which can be run directly in Q2 Oh ~
ps
- RS(204,188)译码器的设计 异步FIFO设计 伪随即序列应用设计 CORDIC数字计算机的设计 CIC的设计 除法器的设计 加罗华域的乘法器设计-RS (204188) decoder design of asynchronous FIFO design application design sequence was pseudo-CORDIC design of digital computer design CIC divider design Le Hua
jsq
- 键盘输入，1062lcd显示，加法、减法（负数不行）、乘法、除法器（若是减法、乘法、除法需先加一次。。。） 初学所写，不足请改进。-Keyboard input, 1062lcd showed that addition, subtraction (not negative), multiplication, division browser (if subtraction, multiplication, division to be added to a...) Beginner boo
m_divider_int
- 14bit pipeline 除法器，在Xilinx V5上可以跑到100M，输出延时3cycles-14bit 100M pipeling divider
converter(D-B)
- 用移位快速实现10进制转2进制，无需除法器-quick converter
Chapter11-13
- 第十一章到第十三章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个
verilog_instance
- 20多个十分实用的verilog例子，如状态机，除法器等-More than 20 very practical verilog examples, such as state machines, divider, etc.
5956447divider
- 基于srt-2算法，利用verilog实现16位定点无符号数除法器（除数、被除数均由16位整数和16位小数组成，商由32位整数和16位小数构成，余数由32位小数组成）-Based on srt-2 algorithm, using verilog to achieve 16-bit fixed-point unsigned divider (divisor, dividend by 16-bit integer and 16-bit decimal form, business from the
chufaqi
- VHDL除法器设计，配合移位减法方式设计除法器以节省硬件成本-VHDL divider design
yunsuan_fig
- 本程序1、2主要是实现简单运算器和除法器的功能，可与C语言等嵌套使用。程序3 实现多选菜单的功能。-1,2 This procedure is mainly to achieve a simple arithmetic unit and the division' s function can be nested with the C language, etc.. Procedures for three multi-function selection menu.
divider
- 高效率的VERIFLOG描述语言的除法器,比一般的速度高-Efficient VERIFLOG descr iption language of the divider, than the average high speed
divider
- 四位无符号二进制除法器的设计,这是整个的工程文档，应该对大家有用-4 unsigned binary division Design
div
- 除法器的电路设计,基本的思想是减法:从最高位(除符号位)开始,减去除数,得到商. -Divider circuit design, the basic idea of subtraction: from the highest bit (except the sign bit), and subtract the divisor, the quotient.
dividerwithoutsignal
- 本程序是实现8位无符号的除法器，得到的结果有商和余数，分别放在两个寄存器变量里面。-divider withoutsignal
fpga_chufaqi
- 基于fpga的32位除法器的设计，开发环境vhdl-Fpga-based 32-bit divider design, development environment vhdl
0101
- Quartus II 除法器，用VHDL语言编写的.除法器。-Divider using VHDL language. Divider
simple_divider
- 自己写的一个除法器，网上多是同一个 繁杂难看明白 自己就写了个简单的 并且很容易看懂-Write a except time-multiplier, online is a multifarious ugly understand oneself write a simple and easy to understand