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diver
- 用VHDL语言产生一个5位数除法器，电子课程设计题目之一-VHDL
divider
- 用VERILOG实现一个被除数为8位、除数为4位的高效除法器-With VERILOG implement a dividend for the 8-bit, 4-bit effective divisor divider
VHDL
- 除法器 4位除法器 可以编程实现 有启发意义-4-bit divider divider can be programmed instructive
VerilogSourceCode
- 乘法器、除法器、多路选择器、编码器、BCD码转换、加法器、减法器、状态机、四位比较器、数码管、串口、跑马灯、电子钟-Multiplier, divider, multiplexer, encoder, BCD code converter, adder, subtractor, state machines, four more players, digital control, serial port, marquees, electronic clock
chufaqi
- 四位除法器：使用vhd实现四位的有符号除法器-Four division: Use vhd signed to achieve four of the divider
zzchufaqi
- vhdl 除法器 eda课程设计用。 设计一个两个五位数相除的整数除法器。用发光二极管显示输入数值，用7段显示器显示结果十进制结果。除数和被除数分两次输入，在输入除数和被除数时，要求显示十进制输入数据。采用分时显示方式进行，可参见计算器的显示功能。-divider vhdl eda curriculum design purposes. Design a two five-digit integer divider division. Enter the value with the lig
hightfrquencydivider
- 用VerilogHDL语言实现一个被除数为8位，除数为4为的高效除法器，实现高效的除法功能-VerilogHDL language with a dividend of 8 bits, the divisor is 4 for the high divider, a high efficiency of the division function
vhdlchufaqi
- 这是一个基于VHDL语言的bch除法器，其功能就是实现二进制除法，采用移位的方式进行-This is based on VHDL language bch divider, its function is to achieve binary division, the way by shift
chufaqi
- 除法器程序，采用Verilog语言编写，并在CPLD开发板上经过验证，正确无误，希望对大家有用-Divider procedure for the Verilog language, and CPLD development board verified and correct, we hope to be useful
div_32bits
- 以ISE为平台，VHDL语言编写的32位补码整数除法器模块，只需在Top模块中调用即可-As a platform to ISE, VHDL language complement 32-bit integer division module, simply call the module to Top
verilog
- 這是一個除法器演算法，是利用移位的方式進行除法運算-This is a divider algorithm is the use of division shift the way
12
- 4位除法器 library IEEE use IEEE.std_logic_1164.all use IEEE.std_logic_unsigned.all entity fpdiv is port ( DIVz: out STD_LOGIC A: in STD_LOGIC_VECTOR (3 downto 0) B: in STD_LOGIC_VECTOR (3 downto 0) data_out: out STD_LO
dcf089f8-85a5-44b9-98d9-e667ba564784
- 除法器能够做除法运算能够做除法运算 除法器能够做除法运算能够做除法运算-Divider can do can do division division
div
- 四位除以四位除法器，VHDL语言描述，quaruts工程-Four divided by four divider, VHDL language descr iption, quaruts Engineering
DIVIDA
- 20位除法器，vhdl语言所写的，不错的代码，仅供参考-20 divider, vhdl language written
zuhe
- 这个是12位的除法器，进过验证的，verilog程序，应用组合逻辑，欢迎下载-This is 12-bit divider, been to verification, verilog, application logic combinations are welcome to download
verilog_Common_arithmetic
- 常用逻辑运算，加法器，乘法器及除法器的verilog语言，可用modelsim或Quartus II 9.0环境-Common logic operation, adder, multiplier and divider verilog language, can be used modelsim or Quartus II 9.0 environment
VHDLchufaqi
- 针对8位的数据进行除法器的设计及实现，最后经编译通过。-Data for the 8-bit divider design and implementation, and finally by the compiler.
diivider4
- 四位除法器，写的算法布扎带，想下就下，不下也行-Four divider, with a written calculation Fabu Zha, think the next on the next, no less will do
chengxu
- 4位乘法器，4位除法器，K倍频的VHDL实现-Four multipliers, four dividers, K multiplier of VHDL