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div
- 两个3位二进制数的除法,结果(整数商)输出到数码管显示-verilog multply
Arithmetic-subroutine-for-sonix-MCU
- 松翰单片机汇编子程序,分单字节乘/除法子程序和双字节乘/除法子程序。-Sonix MCU assembler subroutine, divided into single-byte multiplication/division subroutine and double-byte multiplication/division subroutine.
divider
- 除法器,经过验证,性能优良,值得下载,应该是定点除法的-divider,it is verified and good performance
jisuanqi51
- 51单片机实现4X4矩阵键盘的简单计算:整数之间运算,没有小数所有除法得出的结果不正确,有负号运算,-51 singlechip simple calculation of 4X4 matrix keyboard: an integer between operation, with no decimal all division result is not correct, a minus operation,
add_tree
- 加法树的源代码,是乘法和除法的基础,也即数字电路的verilog基础代码,已经仿真过,完全正确-Adder tree source code, multiplication and division, digital circuit verilog code base simulation entirely correct
MICROCHIP
- 单片机小系统简易计算器设计 设计制作要求:用80C51/52单片机小系统编程制作的简易计算器。 1)要有4位LED显示器。 2)要有0—9个数字输入按键和功能按键分别是 “+”,“-”,“*”,“/”,“=” “CLR”,即“加法”,“减法”,“乘法”,“除法”,“等于”,“清除”。 3)显示过程:实验板通电开机后,第一位LED显示器显示“0”。 按下第一组数字,再按运算键“+ 、- 、*、/ ”后,再按第二组数字,继续按下“=”即可显示整数运算结果。按“清除键”清除当前L
chufa
- 用VHDL设计的四位除法器,可以实现四位二进制数的除法操作-Four divider with VHDL design, you can achieve the four binary division operation
123
- 汇编除法程序,限制用户只能输入数字,回车键会输入确定-Assembly division procedures, limiting the user can only enter numbers, the Enter key will enter the OK
JISUANQI
- 一个用51单片机写的一个简单的计算器程序,可以计算除法有小数点,用矩阵作为按键-A microcontroller with 51 write a simple calculator program can calculate the division has a decimal point, with the matrix as the key
430-SHILICX
- 目录:1. 堆栈时钟初始化 2. RAM自测子程序 3. 二进制转化为BCD码(二进制16位(65536)放R15,结果放R4,R5) 4. BCD码转化为二进制(BCD码放R4,二进制放R5) R5=XO+10*(X1+10*(X2+10*X3)) 5. BCD码转化为二进制(BCD码放R4,二进制放R5)R5=XO+10*X1+100*X2+1000*X3 6. 冒泡排序法(适合20个数字以下) 7. X=a^+b^(a为2个字节,b为2个字节,X为3个字
MSP430--16X16
- 目录:1. 堆栈时钟初始化 2. RAM自测子程序 3. 二进制转化为BCD码(二进制16位(65536)放R15,结果放R4,R5) 4. BCD码转化为二进制(BCD码放R4,二进制放R5) R5=XO+10*(X1+10*(X2+10*X3)) 5. BCD码转化为二进制(BCD码放R4,二进制放R5)R5=XO+10*X1+100*X2+1000*X3 6. 冒泡排序法(适合20个数字以下) 7. X=a^+b^(a为2个字节,b为2个字节,X为3个字
jianyijisuanqi
- 用VHDL实现简易计算器,实现加法、减法、乘法、除法的功能。-Use VHDL to realize simple calculator, can realize the function of addition, subtraction, multiplication, and division.
The-calculator
- 采用51单片机C编写的液晶显示计算器,内容:整数之间运算,没有小数所有除法得出的结果不正确,有负号运算-51 single-chip LCD calculator written in C content: between integer arithmetic, no fractional all divide the result is not correct, there is a negative sign computing
sqrt
- FPGA的一个IP内核,用来优化除法算法的源代码包。-An FPGA IP cores to optimize the division algorithm source code package.
div
- FPGA的IP核中除法算法的源代码,是Verilog语言的,易于初学者的学习。-FPGA IP core in the division algorithm source code, Verilog language, easy for beginners to learn.
MCS-51-subprogram
- 单片机实用程序库,包括数据复制、算术平均滤波、长除法、码制转换、对分查找、浮点运算、三角函数等等。共98页pdf文档。-SCM utility library, including data replication, arithmetic mean filtering, long division, transcoding, bisection search, floating-point arithmetic, trigonometric functions and so on. Total
dividor-design
- 本程序实现了快速除法运算,程序设计简单实用,方便移植-this is a Division
div
- 除法器设计,基于FPGA,实现除法运算,在实物上测试通过-Divider design, based on FPGA, to achieve the division on the physical test
Divider
- xilinx 除法ip核调用 含测试程序 vhdl语言-xilinx ip nuclear division calls including test procedures vhdl language
third
- 用VHDL语言实现了一个有符号除法的程序,用移位相减实现。-Just like