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bkfir2_flp32
- 在ADI的TS系列DSP上编写的32位定点FIR滤波器的程序-in ADI's TS Series DSP prepared on the 32 sentinel FIR filter procedures! !
20070116151416367
- 在ADI的TS系列DSP上编写的32位定点FIR滤波器的程序-ADI in the TS Series DSP prepared on the 32 sentinel FIR filter process
lms
- 1、本试验中未知系统采用25阶的FIR滤波器模拟。其通带边缘频率10kHz，阻带边缘频率22kHz，阻带衰减75dB，采样频率50 kHz。 2、自适应滤波器采用基本LMS算法，滤波器阶数为32，更新步长u为1/(4+xn*xn)。LMS自适应算法参见《现代信号处理》第192页。 已经在DSP2812上实现
MCU_FIR_lowpass
- 通过这个程序，可以更加深入的了解FIR滤波是如何实现的。用AVR单片机 ATMEGA16L实现32阶FIR低通滤波器设计，低通截止频率为200HZ。原始信号经过AD采集后进行FIR运算，处理好的数据通过串口输出。
bkfir2_flp32
- 基于TS201 32 bit Floating Point FIR filter-Based on the TS201 32 bit Floating Point FIR filter
AltrFir32
- 借助于altera公司的IP核，在FPGA中使用dspbuilder实现32位低通FIR滤波器功能，-Altera With the company
case4
- DA算法中的使用的查找表模块，本程序先设计查找表，然后设计4*4DA算法模块，之后进行位扩展和字扩展得到32阶滤波器程序.附带4各表，和FIR滤波器序数-DA algorithm used in the lookup table module, the design of the program first look-up table, and then design 4* 4DA algorithm module, after the word-bit expansion and extens
32chengfa
- 32位乘法，将16位数据和系数扩展32位数，10抽头FIR滤波器-32-bit multiplication, the 16-bit data and coefficient of expansion of 32-digit, 10-tap FIR filter
32jie-vhdl-fir
- 32阶数字滤波器 没有时间来得及精简 不好意思了的说 呵呵 -32-order digital filter is not time enough time to streamline embarrassed to say Oh
32fir
- 32阶滤波器分布式算法实现的主程序代码,用EP2c35f84c8寄存器速率可达243.55MHz-32-order FIR digital filters: 32 filters distributed algorithm order the main program code, register with EP2c35f84c8 rate up to 243.55MHz
fir_comm
- 用QUARTUS软件，实现一个32阶的FIR数字滤波器-QUARTUS software used to implement a 32-order FIR digital filter
fir_da_test
- 用QUARTUS软件，用DA算法实现一个32阶的FIR滤波器-QUARTUS software used with the DA algorithm to achieve a 32-order FIR filter
fpga1244131245d
- 基于FPGA的FIR数字滤波器的设计与实现。滤波器设计参数可实现17阶和32阶线性相位FIR滤波器-FPGA-based FIR digital filter design and implementation. Filter design parameters can be achieved on 17 order and 32 order linear phase FIR filter
FIR_Filter
- verilog的32阶FIR低通滤波器描述-verilog 32-order FIR low-pass filter described
firfilter_32taps
- High pass fir filter with 32 tabs on lpc2148
UseASM_FIR_1MAC
- tms320c5509a汇编程序实现32点fir滤波器，滤除3KHz和8KHz中的低频成分，-Tms320c5509a assembler program realization 32 points fir filter,
fir_asm
- tms320c5509a汇编程序实现32点fir滤波器（利用双累加器实现），滤除3KHz和8KHz中的低频成分，-Tms320c5509a assembler program realization 32 points fir filter (use double MAC realize),
32-order-FIR-on-FPGA
- 基于FPGA的32阶FIR滤波器设计，研究了一种采用FPGA实现数字滤波器硬件电路方案；讨论了窗函数的选择、滤波器的结构以及系数量化问题-32 order FIR filter design based on FPGA, an FPGA implementation digital filter hardware circuit program discussed the choice of the window function, the structure of the filter co
32FIRVHDL
- 基于FPGA的32阶FIR数字滤波器设计 源程序。设计使用了并行乘法器，运行速度更快，占用内存更小，延迟更小。 -32 order FIR digital filter based on FPGA design source program. Design USES parallel multiplier, faster and less memory, less delay.
filter_VHDL
- FIR filter design using VHDL for 32 bit signed coefficientand 32 bit input and decimation is 4 and its working good