搜索资源列表
ppt
- 介绍 AXI 协议的PPT, 和一个 slave（verilog实现） 接口的简单实现，需要的可以看看；-AXI protocol described PPT, and a slave interface is simple to achieve, need to look at
handshake
- AMBA 3 AXI handshake protocol. Verilog platform. master and slave.
AMBA
- SystemC写的AMBA 3.0 AXI总线事物级TLM模型 正在调试。有详细实验报告说明。-AMBA 3.0 AXI TLM SystemsC
BP062-BU-01000-r0p0-00rel0[1][1].tar
- AXI协议检查器，由ARM公司开发对于想开发AXI master和slave模型的ASIC设计人员非常有用！-AXI protocol checker, developed by ARM to develop for the AXI master and slave model is very useful ASIC designers!
AMBA_axi_classic_protocol_document
- AMBA axi经典协议文档值得参考学习的资料AMBA axi classic protocol document-AMBA axi protocol documentation is also useful to study classical information AMBA axi classic protocol document
Axi_mux
- The elements come from the necessity of creating generic modules, in the verification phase, for this widely used protocol. These primitives are presented as a not compiled library written in SystemC where interfaces are the core of the lib
Micrium_Microblaze_uCOS-II-AXI
- 支持xilinx ise designer 14.x的microblaze AXI总线 ucosii操作系统。-Support xilinx ise designer 14.x for microblaze AXI bus ucosii operating system
microzed-axi-dma
- microzed (zynq) axi dma source vhdl
zc706-axi-dma-fifo-master
- zc706 axi-dma-fifo-master example
axi_lite_user
- axi_lite_user官方样例，精简功能，适用于zynq系列axi总线(Axi_lite_user official sample, streamline function, apply to zynq series Axi bus)
axi_ipif_v2.3
- The AXI4-Lite IP Interface (IPIF) is a part of the Xilinx family of Advanced RISC Machine (ARM) Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface (AXI) control interface compatible products. It provides a point-to-point
AXI slave
- 使用verilog语言实现了AXI总线通信协议的从机部分(The slave part of AXI bus communication protocol is realized by using Verilog language)
slave
- xilinx Zynq 中的AXI总线 axi slaver模块(AXI bus Axi slaver module in Xilinx Zynq)
axi_dma
- 在zedboard开发板上采用vivado通过AXI进行DMA数据传输(Using vivado to transfer DMA data through AXI on zedboard development board)
AXI-HP-ZYNQ
- 用Vivado IPI搭建的Zynq-7000 PS到PL通信过程，使用了AXI-HP接口，利用AXI-DMA IP实现直接读写DDR的过程，软件可以配置传输尺寸。(The Zynq-7000 PS to PL communication process is built by Vivado IPI. AXI-HP interface is used, and AXI-DMA IP is used to read and write DDR directly. The software can
AMBAaxi
- amba axi specification
axi_slave
- amba总线中axi的slave部分，用verilog实现的slave.(The slave part of Axi in the AMBA bus, slave. implemented with Verilog)
AXI-full
- axi协议中的full子协议，可用于直接访问zynq器件的ddr器件。(The full sub protocol in the Axi protocol can be used to direct access to the DDR device of the zynq device.)
my_led_ip
- 四通道axi LED灯控制器，用于嵌入式系统中的一些功能指示(The four channel Axi LED lamp controller is used for some function instructions in the embedded system)
verilog-axi-master
- Verilog AXI Components Readme GitHub repository: alexforencich verilog-axi