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CHENGFAQI
- 本源码是高速并行乘法器的设计源码，开发软件为MAX+PLUS.输入为两个带符号的二进制数-the source is a high-speed parallel multiplier design source, development of software for MAX PLUS. with the importation of two symbols of binary -
chengfaqi
- 乘法器,实现了乘法和除法的功能,能够进行32位的运算-Multiplier to achieve the functions of multiplication and division to carry out 32-bit computing
chengfaqi
- 乘法器 靠移位实现，其中包括一些创新的思想，把vhdl和c语言的区别区分开来-Multiplier achieved by displacement, including some innovative thinking, and c to vhdl language to distinguish the difference between
chengfaqi
- VHDL24*24位无符号乘法器，采用的是18*18结构-VHDL24*24-bit unsigned multiplier, used in the structure of 18* 18
chengfaqi
- 一个乘法器，比较简单，但也是自己认真写的，上传上来了-hahahhahhahha
chengfaqi.doc
- 设计一个两个5位数相乘的乘法器。用发光二极管显示输入数值，用7段显示器显示结果。乘数和被乘数分两次输入(verilog语言实现)-Design a multiplier of two 5-digit multiplication. Enter the value with the light-emitting diode display, with 7-segment display shows the results. Multiplier and the multiplicand input
chengfaqi
- 基于FPGA采用时序逻辑方法设计的16位乘法器代码-FPGA-based temporal logic designed using 16-bit multiplier code
chengfaqi
- verilog语言编写的一个乘法器程序，是16位相乘！已通过仿真，用Quartus II 9.1 编写-a multiplier verilog language program, is 16 multiplied by! Through simulation, the Quartus II 9.1 to write
chengfaqi
- 通过verilog hdl语言实现伽罗华域GF（q）乘法器设计-By verilog hdl language Galois field GF (q) Multiplier
chengfaqi
- 基于fpga的乘法器设计 已经验证请放心下载-Fpga-based multiplier design has been verified, please rest assured download
chengfaqi
- 基于51单片机的乘法器，含proteus仿真，用keilC编译的，代码详细，含有注释，望点个赞，谢谢，头文件全，方便移植。-Based on 51 single-chip multiplier, with proteus simulation, using keilC compiled code in detail, contains notes, looking like a point
chengfaqi
- 乘法器设计，仿真文件也包含在其中，供学习使用-Multiplier，you can use it
chengfaqi
- 完成该3位3位的乘法器,把乘法问题转化为逻辑“与”运算和加法运算。-The completion of the 3 3 bit multipliers, the multiplication problem is transformed into a logic and operation and the addition operation.
chengfaqi
- 利用51单片机和按键实现乘法器的功能，按键所按数值会在串口中显示出来，并且能在串口中得到作乘法之后的结果-Use SCM and realize multiplier function keys, press the numeric keys are displayed in the serial port, and can be obtained as a result of the multiplication of the serial ports later
chengfaqi
- 数字电路中实现八位二进制乘法器的VHDL代码-Digital Circuit achieves eight binary multiplier VHCDL code
chengfaqi
- 16位的原码两位乘法器，实现原码两位乘，经试验可以使用-16 of the original code two multiplier, two implementation source code
booth
- 16位booth乘法器的实现：先将被乘数的最低位加设一虚拟位。开始虚拟位变为零并存放于被乘数中，由最低位与虚拟位开始，一次判定两位，会有4种判定结果。(The 16 bit booth multiplier to achieve: first the least significant bit is added with a virtual position. Start a virtual becomes zero and stored in the multiplicand, startin