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DCT_1D
- 一维DCT变换的verilog源码,可用于JPEG算法优化的参考。程序中用到的算法称为“扭卷积”,可参考相关IEEE paper
JPEG
- 本文首先介绍了静态图像压缩(JPEG)编码算法的基本原理、压缩的实现过程及其重要过程的离散余弦变换(DCT)算法的实现原理及软件实现的例程,其次着重介绍了压缩过程中的DCT、量化和编码三个重要步骤的实现原理。-This paper describes the static image compression (JPEG) coding algorithm is the basic principle of compression process of the implementation pro
Chapter6-9
- 第六章到第九章的代码 本书通过100多个模块实例,详细地讲解了Verilog HDL程序设计语言,全书共分13章,内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等,实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例
DCT
- ARM汇编,实现DCT算法,图像压缩,JPEG 需要loadmemory,里面附带load文件示例以及样子图片,raw格式-ARM compilation and realizing DCT algorithm, image compression, JPEG need loadmemory, incidental load inside sample documents, as well as look like picture, raw format
jpeg.tar
- This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with 2:1:1 subsampling, able to compress at a rate of up to 24 images per second (on XC2V1000-4 @ 40 MHz with resolution 352x288). Image resolution is no
DCT_IDCT
- verilog code for DCT and IDCT (JPEG)
dct
- JPEG Compression and Ethernet Communication on an FPGA
JPEG_WEBINAR
- JPEG DCT C 代码,可在Catapult下生成VHDL -JPEG DCT C code for VHDL generation in Catapult
jpeg_hardware.tar
- 用FPGA实现的JPEG压缩器,可以直接使用,内含完整文档说明-This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with 2:1:1 subsampling, able to compress at a rate of up to 24 images per second at the maximum resolution 352x288 (on XC2V
fpga-jpeg
- 包含DCT变换,RGB2YCBCR,JPEG等多个verilog代码及工程-Contains DCT transform, RGB2YCBCR, JPEG and many other verilog code and project
JPG
- Implementing the YCBCR and DCT stage of jpeg encoding
dct
- DCT 2d for JPEG in verilog