搜索资源列表
ref-sdr-sdram-vhdl
- DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M
leon3-altera-ep2s60-ddr
- This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOT
DDR-SDRAM_IP_core
- DDR-SDRAM接口模块verilog源代码，可用作IP核使用，已在FPGA上验证-DDR-SDRAM interface module verilog source code, can be used as IP cores to use, proven
simulator
- 开源的基于SystemC的模拟器，可以模拟ARM CPU, Cache, DDR，NOR, NAND, 时序和功耗均可以正确模拟。-This simulator is a cycle-accurate system-level energy and timing simulator. Developed by Embedded Low-Power Laboratory, Seoul National University. The simulator’s underlying kernel is
1
- PCIE 与DDR的接口范例，由altera提供-PCIE and the DDR interface examples provided by the altera
xapp860
- 16通道DDR的LVDS接口（VHDL,Verilog and doc）-16-Channel, DDR LVDS Interface with Real-Time Window Monitoring
c_xapp260
- xilinx应用指南xapp260的中文翻译版本。利用 Xilinx FPGA 和存储器接口生成器简化存储器接口。本白皮书讨论各种存储器接口控制器设计所面临的挑战和 Xilinx 的解决方案，同时也说明如何使用 Xilinx软件工具和经过硬件验证的参考设计来为您自己的应用（从低成本的 DDR SDRAM 应用到像 667 Mb/sDDR2 SDRAM 这样的更高性能接口）设计完整的存储器接口解决方案。-The use of Xilinx FPGA and Memory Interface Gen
c_xapp858
- 这是xilinx应用指南xapp858的中文版本。本应用指南介绍了用于实现高性能 DDR2 SDRAM 接口的控制器和数据采集技术。本数据采集技术使用了每一个 Virtex™ -5 I/O 都具有的输入串行器/ 解串器 (ISERDES) 和输出双倍数据速率 (ODDR) 的功能。-This is the xilinx application note xapp858 the Chinese version. This application note describes the i
Dx0520soure
- WINCE下面的的DDRAW用户界面程序可以实现动画效果呀,是DDRAW界面编程的好例子-WINCE following the DDRAW user interface programs can achieve animation ah, is a good example of programming interface DDRAW
DDR_prj
- DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA。-DDR controller VHDL source code. FPGA implementation using DDR interface controller for Altera' s FPGA.
DDR_rev0.2
- DDR memory interface for PNX8935, PNX8932, PNX8335, PNX8332
DDR_SDRAM_design_and_conclusion
- DDR SDRAM总结文档，描述了DDR IP的设计挑战，接口时序，模块设计原则，调试技巧及应用指南-DDR SDRAM summary document describing the design challenge of DDR IP, interface timing, modular design principles, debugging skills and Application Guide
DDR-with-CoolRunner-II
- 详细讲解了CoolRunner II CPLD与DDR SDRAM的接口设计-Explained in detail about the design of the CoolRunner II CPLDs and DDR SDRAM interface
ddr_sdr_latest[1].tar
- ddr sdram 控制器的接口，为工业标准化存储设备提供简单的接口-The DDR SDRAM Controller provides the user with a simplified interface to industry standard memory devices. Using this controller makes accesses to DDR SDRAM devices as simple as possible.
emi(1)
- the external memory interface for the ddr ddr2 ddr3 sdram device
ddr_ctrl
- 攒人品上传多年工作积累代码。主要功能是ddr memery controler interface等控制。可以综合。-Save the character to upload the accumulation of many years of working code. The main function is to ddr memery controler interface control. Can be integrated.
sdram
- SDRAM 接口程序，里面涵盖 datasheet，原理容易懂，对学习ddr有兴趣的可以下来看看。-SDRAM interface program, which covers the datasheet, easy to understand the principle of learning ddr can look down.
RS485_R
- 达芬奇系列开发板，rs485测试程序，用于检测DSP的rs485接口工作正常-Da Vinci series development board, DDR test program, used to detect between Dsp and rs485 interface to work normally
6678
- 集成6678以太网，NANDflash，DDR，定时器，等常规接口的初始化及应用实例。-6678 integrated Ethernet, NANDflash, DDR, timers, and other initialization and application examples conventional interface.
AXI-HP-ZYNQ
- 用Vivado IPI搭建的Zynq-7000 PS到PL通信过程，使用了AXI-HP接口，利用AXI-DMA IP实现直接读写DDR的过程，软件可以配置传输尺寸。(The Zynq-7000 PS to PL communication process is built by Vivado IPI. AXI-HP interface is used, and AXI-DMA IP is used to read and write DDR directly. The software can