搜索资源列表
des_Vhdl
- VHDL & Verilog Synthesizable model of the Data Encryption Standard (DES)
DES
- 用vc++实现des算法，此算法主要实现简单的明文加密、解密-Des algorithm with explicit encryption, decryption! ! !
0470863358
- programmation des PIC
des_8051
- DES encryption/decryption used in 8051
mos_des
- DES算法的verilog实现，可以研究下。-DES for Verilog。
key
- 用vhdl语言实现des编码中的密钥产生 是des编码中重要的一部分-Des code using vhdl language in the key generation is an important part des coding
LIP1602CORE_des
- Verilog DES Encrption Module
DES
- 国产32位CPU，SSX45芯片的DES功能模块程序-des function module for SSX45 Chip
Allumer-des-led-
- code assembleur pour allumer des led alternativement -code assembleur pour allumer des led alternativement
Description-of-DES-with-VHDL
- 用VHDL描述DES算法 用硬件的方式DES加解密 体现了硬件编程人一般思想-DES algorithm using VHDL descr iption of the way with hardware DES encryption and decryption hardware programming reflects the general thinking of people
SIMULATION-AND-SYNTHESIS-OF-TRIPLE-DES-BLOCK-CIPH
- SIMULATION AND SYNTHESIS OF TRIPLE-DES BLOCK CIPHER USING VHDL
FPGA-BASIC-DES
- 采用vhdl实现DES算法，有详细的设计理论。为电子科技大学研究生论文。-VHDL realize the use of DES algorithm, a detailed design theory. For the University of Electronic Science and Technology Graduate thesis.
DES
- 基于51的DES算法源程序，包括上位机验证DES算法工具，可直接应用于项目中-51 DES algorithm, source code, including the host computer to verify that the DES algorithm tool can be applied directly to the project
des-mac
- CPU卡的计算DES,MAC的程序，实际验证过，可用-CPU card calculations DES MAC program, the actual verification that can be used
des加解密算法
- MFC\C51下的des加解密算法，适用于嵌入式应用
keil des
- 可以在keil c，下完美运行。试过。 DES加密。 是否有解密没有试过。
SIMULATION-AND-SYNTHESIS-OF-TRIPLE-DES-BLOCK-CIPH
- This project presents FPGA implementations of the DES and Triple-DES with improved security against power analysis attacks. The proposed designs use Boolean masking, a previously introduced technique to protect smart card implementations from these
des
- des的Verilog代码（已编译，可直接使用）-des Verilog code (compiled, and can be used directly)
DES
- 该源码采用DES加密标准，采用Verilog编写，时钟为50M，可以扩展为硬件级加密系统-The source uses DES encryption standard, Verilog prepared, the clock is 50M, can be extended to hardware-level encryption system
DES
- Data Encryption Standard(DES) VHDL Source Code