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pll.rar
- 模拟锁相环（apll）的一些simulink模型,Analog phase-locked loop (apll) some simulink model
PLL
- 用VHDL和matlab编写的数字锁相环电路。-Matlab with VHDL and digital phase-locked loop circuit prepared.
shu-si-fuo-xiang-huan
- 该压缩文件是一个用matlab实现数字锁相环仿真的程序-The compressed file is a digital PLL with matlab simulation program