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课题:计数式数字频率的CPLD实现.rar
- 本设计的基本要求是以复杂可编程逻辑器件CPLD为基础,通过在EDA系统软件ispDesignExpert System 环境下进行数字系统设计,熟练掌握该环境下的功能仿真,时间仿真,管脚锁定和芯片下载。 本系统基本上比较全面的模拟了计数式数字频率计,广泛应用于工业、民用等各个领域,具有一定的开发价值。
protel99中文教程
- 这是一本学习vhdl语言以及EDA的好书,适合初学者,我强力推荐-This is a learning and EDA VHDL language books, suitable for beginners, I strongly recommend
Verilog HDL练习题
- 硬件描述语言,对学习EDA的人,特别是初学者都有很大的参考价值。-hardware descr iption language, to learn the EDA people, especially beginners have great reference value.
基于CPLD-FPGA的半整数分频器的设计
- 基于CPLD-FPGA的半整数分频器的设计,用于设计EDA-based CPLD-half FPGA integer dividers in the design, design for EDA
同步复位与异步复位问题
- 同步复位与异步复位问题,应用于EDA设置,适合初学者-asynchronous and synchronous reset reduction, EDA application settings for beginners
数字频率合成器的FPGA实现
- 在EDA中,基于数字频率合成器的FPGA实现-in EDA, based Digital Frequency Synthesizer FPGA
edajishu
- EDA基础教程-EDA based tutorial.
autosellmachine
- 用VHDL语言编写的自动售货机程序,下载到EDA实验板上可实现基本的买货售货找零显示总钱等功能。-VHDL prepared by the vending machine procedures, Experimental downloaded to EDA board can achieve basic placing orders showed total sales through irregular money functions.
jiaotd
- AD0809的源程序,能使EDA工具箱显示AD0809,具备树模转换功能-AD0809 a source, EDA can show AD0809 a toolbox, with tree-analog converter function
VHDL3
- 这是一个自动售货机的vhdl源码,曾经是eda比赛的题目,供大家参考。-This is a vending machine in VHDL source code, the game had been sown topic, for your reference.
EDATOOL
- EDA的工具介紹(WORD檔)<沒有解壓縮密碼>-introduced EDA tools (Word stalls) lt; No extract passwords gt;
51asmbase
- 精品电子资料,精品EDA软件下载,精品单片机教程,精品电子知识文摘, 精品网站源代码,精品教学文章,精品建站素材-electronic information products, excellent EDA software download, boutiques SCM Guide, boutiques electronic knowledge Digest, boutiques website source code, excellent teaching articles, th
vhd
- 基于maxplusII的EDA设计,自动绕线机的设计源程序。-maxplusII Based on the EDA design, automatic winding machine design source.
24wei10jinzhiPINLVJI
- 可编程逻辑设计的程序!24位十进制频率计!可使EDA实验年箱测量指定频率!-programmable logic design process! 24 metric Cymometer! EDA will experiment, measurement designated frequency bins!
jp
- led灯按顺序显示,EDA课程实验,verilog语言(EDA experiment with Verilog language)
y210
- 三八译码器,四位加法器,EDA实验,用verilog编写(EDA experiment with verilog language)
clock1
- 时钟显示程序,EDA实验,用verilog语言编写(EDA experiment with verilog language)
4位全加器 计数器等程序
- EDA仿真工具使用的,进行EDA开发的多个程序; 包括:4位全加器,12分频,128分频,篮球计数秒表(部分),计数器; 可以搭配EDA仿真软件使用,也可以搭配开发板使用;(EDA simulation tools used for EDA development of multiple programs; Including: 4 bit full adder, 12 frequency division, 128 frequency division, basketball cou
NEW
- Verilog投币式手机充电仪 清华大学数字电子技术基础课程EDA大作业。刚上电数码管全灭,按开始键后,数码管显示全为0。输入一定数额,数码管显示该数额的两倍对应的时间,按确认后开始倒计时。输入数额最多为20。若10秒没有按键,数码管全灭。(Verilog coin operated cell phone charger EDA major homework of digital electronic technology foundation course, Tsinghua Un
EDA-2
- 数字电子技术基础课程的第二次EDA作业,内容是投币充电仪。(The second EDA assignment of basic course of digital electronic technology is coin charger.)