搜索资源列表
afifo_0916
- 异步FIFO，使用XILINX产品实现，可以通过改参数来重新修改深度和位宽-Asynchronous FIFO, using the XILINX product realization, you can change parameters to re-modify the depth and Width
DSP2812FIFO
- DSP上实现 软件FIFO队列 提高SCI的数据缓冲能力-DSP to achieve the software improve the SCI data FIFO queue buffering capacity
async_fifo
- verilog HDL写的异步fifo代码及测试平台，直接可用，可生成RTL代码-asynchronous fifo write verilog HDL code and test platform, directly available, can generate RTL code for
arlut_fifo_interface
- fifo控制器，可以加到nios系统下，通过nios进行FIFO的读写，经过本人的项目验证-fifo controller, can be added to the nios system, through the nios to FIFO read and write, after I verified the project
dsp_circular_buffer.tar
- FIFO circular buffer for DSP
FIFO
- here is realized simple FIFO stack in vhdl. very simple example, but very helpful.
fifo64x8_tb
- Testbench for Xilinx 64x8 FIFO.
FIFO
- C语言实现的FIFO C语言实现的FIFO -C语言实现的FIFO
fifobaseddprammemory
- This file if about DPram based fifo storage... wirte and read in both ports
pgm
- uart vhdl code contains all the neceesary things for a uart of speed 2 mbps and has a fifo of 64 KB
c22-trunk
- Silabs 8051f040 device project. Contains example of: CAN, FIFO stack, Scratch FLASH ROM, GPIO, Modbus slave, self reprogram internal FLASH on-the-fly, WDT, Timers, UART0, Xmodem.
FIFO
- common FIFO module and it is easy to involve in ur design.
fifo.v
- This the source code for FIFO -This is the source code for FIFO
multiproc-fifo
- Arm嵌入式系统,进程间通信的一个C语言程序！-ARM programming, multiple process communication!
DSP6713
- 包括定时器、SPI、SDRAM、Flash、FIFO等程序，均调试通过-SPI\SDRAM\Flash\FIFO\timer for DSP6713
fifo2
- 异步双时钟fifo，vhdl源代码。基本组成是定制的fifo加上空满判断逻辑，基本功能都有-Asynchronous dual clock fifo, vhdl source code. Fifo basic component is a custom air filled with the logic to judge the basic functions are
sdcard_mass_storage_controller_latest.tar
- 基于wishbone总线的SD Card IP Core,有Verilog和VHDL两种语言版本,包含了FIFO和DMA两种实现方式,是开源的IP Core-Based on the wishbone bus SD Card IP Core, there are two language versions of Verilog and VHDL, including the FIFO and DMA implemented in two ways, is open source IP Core
new_fifo
- 最新的testbench of FIFO ，使用Vmm，VCS，可以大致了解一下VMM的体系-the new fifo VMM testbench
fifo
- 单片机FIFO操作子程序，可应用于各类FIFO操作-FIFO operation functions