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DSP做的视频处理系统中FIFO问题解答
- DSP做的视频处理系统中FIFO问题解答-DSP video processing system FIFO Questions
fifo数据缓冲器的vhdl源程序
- 编了个8*8位的fifo数据缓冲器的vhdl源程序,是经过quartusII4.2编译成功的程序。。希望能跟各位交流-Bianlegan 8 * 8 of the data buffer fifo VHDL source, after quartusII4.2 compiler successful procedures. . Hope you enjoy the exchanges
fifo程序
- 用verilog语言在fpga中实现fifo功能!-using Verilog language in which they simply realize fifo function!
fifo
- 一个简单的FIFO实现,基于STM32的UART+DMA方式。(A simple FIFO implementation, based on the STM32 UART+DMA approach.)
fifo
- 异步FIFO 输入: 16bit 输出:16bit 深度:256(Asynchronous FIFO Input: 16bit Output: 16bit Depth: 256)
FIFO
- 用verilog语言的实现FIFO存储器,以先进先出的方式处理数据(The FIFO memory is implemented in Verilog language, and data is processed in FIFO)
Synchronous FIFO
- 用16*8 RAM实现一个同步先进先出(FIFO)队列设计。由写使能端控制该数据流的写入FIFO,并由读使能控制FIFO中数据的读出。写入和读出的操作由时钟的上升沿触发。当FIFO的数据满和空的时候分别设置相应的高电平加以指示(mplementation of a synchronous first in first out (FIFO) queue design with 16*8 RAM. A write FIFO that controls the data stream by writi
FIFO
- FIFO的功能众所周知,非常好的处理时序问题。(The functions of FIFO are known to be very good at dealing with timing problems.)
FIFO Design Using Verlilog
- DFF with fifo concepts
FIFO Details
- FIFO Design PDF files
OV7670+FIFO+3.0TFT
- ov7670 + FIFO原理,入门,简述,应用(Ov7670 + FIFO principle, introduction, brief descr iption, application)
fifo
- 每一个时钟(clk_100m)上升沿,判断写请求信号是否为高电平,如果为高电平,那么就将数据线上的数据写入FIFO,然后在下一个时钟上升沿,wrf_use增加1,表示FIFO队列里的数据增加了一个。 细心的朋友可能会发现,其实在这一过程中,读请求信号一直为高电平,仔细分析这两张图片,大概可以得出如下判断: 在每个读时钟的上升沿,首先判断读请求信号是否为高电平,若为高电平,再判断FIFO是否为空,如果不为空,那么在下一个read_clock的上升沿将数据读出(us QuartusII desi
Asynchronous FIFO Architectures
- 老外的经典异步FIFO结构讲解,一共三个部分。(Asynchronous FIFO Architectures Vijay A. Nebhrajani)
fifo
- 基于verilog HDL的fifo设计与测试,包含设计与测试代码,以及简单的makefile编写。整个平台是基于linux操作,仿真平台是基于SYNOPSYS的vcs工具。(Based on verilog HDL fifo design and testing, including the design and test code, and simple makefile.The platform is based on Linux operating, the simulation pla
无FIFO摄像头 DMA传送
- 该程序是使用了无fifo的7670摄像头,使用dma传输方式,能够稳定传输图像(The program uses a FIFO - free 7670 camera and uses DMA transmission to stabilize the transmission of the image)
FIFO
- FIFO code in verilog
异步FIFO
- 自己编写的同步和异步FIFO的verilog代码,验证过,有可靠性(Verilog code of my own synchronous and asynchronous FIFO, verified,and reliable.)
fifo
- fifo模块,改模块使用同步fifo设计,里面包含一些设计技巧,读延迟最少(The module of FIFO is modified by using synchronous FIFO, which contains some design skills and the least latency.)
(FIFO)串口接收和发送
- 使用stm32的串口实现fifo队列缓冲读写数据,值得新手学习(Using STM32 serial port to realize FIFO queue buffer read and write data, it is worth learning by novice.)
异步FIFO
- 纯Verilog实现的异步FIFO,分为读写控制模块,SRAM CORE,同步等几个模块,内含源文件和仿真文件(The asynchronous FIFO implemented by Verilog is divided into read-write control module, SRAM core module and synchronization module)