搜索资源列表
robot
- fifo接收并口数据并转换为6路脉冲发送-fifo received and converted to parallel data transmission 6-channel pulse
syn_fifo_use
- fpga 同步fifo调用 vhdl语言编写syn fifo use -synchronous fifo call fpga vhdl language syn fifo use
CummingsSNUG2002SJ_FIFO2
- Simulation and Synthesis Techniques for Asynchronous FIFO Design2
lpc23xx-ucosii-xx_test
- 基于LPC2366的ucos移植，集成3个版本的ucos，根据需要条件编译即可，添加串口fifo操作，串口通信非常流畅-Integration of three versions of ucos, conditional compilation can, according to need to add a serial port fifo operations, a serial port communication is very smooth!!!!!!!!!!!!!!!!!!!!!
LM3S_UART_FIFO_IntTx
- UART(通用异步收发器)\LM3S系列UART例程：FIFO中断方式发送数据-UART (Universal Asynchronous Receiver Transmitter) \ LM3S series UART routines: FIFO interrupt mode to send data
moshuzhuanhuan1111
- 模数转换，将8路并行的数据缓存在FIFO中，再输出。通过时序控制A/D芯片的采集速度，和ARM板的接收速度。-Analog-to-digital conversion, eight road parallel data cached in FIFO, and output. By sequential control of A/D chip acquisition speed, and ARM board receives the speed.
LATTICE_ASYNFIFO
- LATTICE FPGA FIFO 程序例程，工程详细，全部源代码上传 -LATTICE FPGA FIFO routine, detailed engineering, all source code uploaded
VGA800
- 本代码用verilog语言，配合quartus里自带的fifo来简单实现vga显示屏的操作，重点在于弄清楚时序。代码中被注释的部分也可以用于彩色条纹的测试。-The code to use verilog language, with quartus in fifo comes to simply achieve vga screen operation, with emphasis on clear timing. The code portion of the notes can be te
EZ_USB_LOOPBACK
- 本程序：EZ-USB在slave fifo模式下，利用FPGA控制EZ-USB的数据读写-This program: EZ-USB in slave fifo mode, use the EZ-USB FPGA control data read and write
SDRAM_Test5
- 基于EP1C12Q240C8的红色飓风二代FPGA开发板的SDRAM测试程序，含有写入和读出FIFO，串口UART,数据发生模块。-Based EP1C12Q240C8 a red hurricane II FPGA development board SDRAM test program, containing written and read FIFO, serial UART, data generation module.
uartfifo
- 一个基于verilog的fifo的例子，由数据产生模块产生数据传到fifo中，然后同过发送模块将数据发到上位机上。-One based on the fifo verilog example, by the data generation module generates data to the fifo, and then sent over the same module sends data to the host computer.
STM32_KeyScan
- 基于奋斗开发板的STM32的按键控制LED灯，使用状态机思想消除按键抖动并加入了长按处理功能，用16位FIFO（数据缓冲队列）提高可靠性和可移植性-STM32 development board based on the struggle of the keys to control LED lights, using a state machine debounce ideology and joined the long press processing functions, using 1
2440project
- 改压缩包包括了ARM9中的 所有裸机部分程序，有GPIO,UART,FIFO,DMA,NOR FLASH,NAND FLASH,LCD等，这些程序都在FriendlyARM的Mini2440开发板上进行了验证-GPIO,UART,FIFO,DMA,NOR FLASH,NAND FLASH,LCD
20131010-code
- fx2lp 68013 xilinx XC3s400 实现slave fifo通讯，包括68013的固件以及fpga的代码（verilog）。摸了好久才调试通过的，特共享出来解救苍生！-fx2lp 68013 xilinx XC3s400 slave fifo
FPGA2-DSP2-EDMA
- 例程是FPGA通过EMIF给DSP发送数据，里面包含了一个简单的状态机和一个基于IP核的fifo，适合初学者-Routine is the FPGA to send data to the DSP via EMIF, which contains a simple state machine and an IP-based core fifo, suitable for beginners
UART2_4F120
- 从运行超级终端的计算机上运行测试UART0并实现双向数据转移。这一次，我们使用了中断和FIFO。-Tests the UART0 to implement bidirectional data transfer to and from a computer running HyperTerminal. This time, interrupts and FIFOs are used. U0Rx (VCP receive) connected to PA0 U0Tx
tb_asy_fifo
- the testbench of asynchronous fifo-test the logic function of asynchronous fifo
FIFO_test
- EP2S90 与 TMS320C6727 进行32位通信时读写FIFO的程序，测试完美通过-EP2S90 read FIFO is performed with the TMS320C6727 32-bit communications program, a perfect test by
YJ_EP4
- 与Cpress CY8013所对应的 FPGA端的开发 使用NIOSII NIOSII 连续往USB FIFO 端点里灌数据 上位机不断的接收 陪和我的上位程序可以达到30Mbyte/s 需要上位机程序的去搜索TestUSBSpeedMFCNovember -upload-And Cpress CY8013 corresponding end FPGA development using NIOSII NIOSII continuous irrigation to USB FIFO
uart_fifo
- 带fifo的串口通信verilog设计，该设计为学习uart所用，完成PC端发送至fpga后fpga原数据返回，支持长字符串。-Serial communication with fifo verilog design, which is used to learn uart complete PC sends data back to the original post fpga fpga, support long strings.