搜索资源列表
13
- para13： fifo.vhd FIFO（双口RAM） fifo1.vhd FIFO（嵌入式EAB） fifo2.vhd FIFO（LPM）-para13: fifo.vhd FIFO (dual port RAM) fifo1.vhd FIFO (embedded EAB) fifo2.vhd FIFO (LPM)
CuFIFO
- fifo的vhdl代码,比较简单，适合初学。-fifo the VHDL code, is relatively simple, suitable for beginners.
FIFO1
- FIFO存储电路的设计与实现，用verilog实现fifo的参考设计-FIFO memory circuit design and realization of the realization of fifo with Verilog reference design
fifo
- 先入先出缓冲存储器，采用verilog hdl-FIFO buffer memory, using verilog hdl
2812SPIFIFO
- 使用spi fifo中断进行接受和cputimer中断里进行发送-Carried out using the spi fifo interrupt acceptance and interrupt cputimer conducted Send
ASYNCFIFOXPXMOD
- 任意时钟配比的异步fifo.含有synplify ip库中的双端口ram。用于处理多时钟域问题。-Arbitrary ratio of asynchronous clock fifo. Containing synplify ip library of dual-port ram. Used to deal with the issue of multi-clock domain.
usbin_v1.7
- 用于cy7c68013与fpga的从FIFO通讯.版本1.7-For the CY7C68013 and FPGA communications from the FIFO. Version 1.7
AS_FIFO_DESIGN_Verilog
- 使用Verilog硬件描述语言完成了一个异步FIFO的设计，供相关硬件开发人员参考。-Verilog hardware descr iption language used to complete an asynchronous FIFO design, hardware development for the relevant reference.
fifo_src
- verilog语言实现，利用BlockRAM实现FIFO。-Verilog language, the use of BlockRAM achieve FIFO.
AutoFIFO
- EZ-USB的CY7C68013A实现Slave FIFO的AutoIN。关键配置见TD_Init函数。-EZ-USB
FIFO_2
- VERILOG Synchronous FIFO. 4 x 16 bit words.-VERILOGSynchronous FIFO. 4 x 16 bit words.
ImplementingFIFO-GPIF
- USB 2.0 FIFO 工作模式 C语言编程 CY7C68013单片机-USB 2.0 FIFO mode of C language programming CY7C68013 Singlechip
75448172geleicounter
- 这是异步fifo的vhdl实现代码，已经在FPGA上通过实践证明，运行状态良好-This is the asynchronous fifo realize the VHDL code has been adopted in the FPGA Practice has proved that running in good condition
Serial_FIFO_LPCARM
- LPCARM串口无限FIFO的实现源码。-Serial LPCARM unlimited source implementation of the FIFO.
fifo
- simulation fifo protocol
USB
- VC5416 对USB寄存器的读／写、配置； VC5416 对 USB的 FIFO 的操作； VC5416 对 USB的 setup 包的操作； VC5416 对 USB的 Endpointo 的操作；-VC5416 of USB register read/write, configuration VC5416 on the USB-FIFO operation VC5416 for USB operation of the setup packet VC5416
connect20090223
- fpga从FIFO读数据并上传到双口ram中。-FPGA read data from the FIFO and upload it to dual-port ram Medium.
ram
- a 16 by 4 ram is used for many applications as a basic component such as fifo and stack etc
rtl
- 液晶model 设计LCD 并口模式下的仿真model-LCD FIFO model