搜索资源列表
bstop
- EVM板话音扰码器，使用-D命令展开 C54X带通滤波器汇编文件 -EVM voice scrambler, use-D start C54X order band-pass filter compilation
scrambler
- 通信系统中的加扰与解扰程序，用verilog语言实现，有波形文件可以直接查看功能
pn_code
- 系数为4的扰码生成器，并每四位扰码产生一个触发串并转换的触发信号，可用于4b/5b编码的触发信号。verilog程序，带test程序-coefficient of the four scrambler generator, and every four scrambler have triggered a string conversion and the trigger signal can be used to trigger 4b/5b coding signal. Verilog pro
screw
- 一个好用的扰码器，主要用在光纤通信上面。因为为了保持送给光模块的信号不是全1或者全0-A nice scrambler, mainly used in optical fiber communication above. Because in order to maintain the optical module of the signal is not sent to all 1 or all 0
scrambler_17
- this parallel scrambler verilog code -this is parallel scrambler verilog code
scrdsc64
- a simple project with 64 bit scrambler as data encryption/decryption
SCRAMBLER
- 32位扰码器的verilog代码，编译通过-The Verilog code of 32_bit scrambler
DATA_scramble
- 扰码器的verilog实现,参考802.11a相关标准-Scrambler in verilog implementation
Scrambler
- Scrambler most widly used an data transfer operation in PCI.
LANE0REGISTER
- The purpose of the Lane register is to get the TLPs or DLLPs from the Byte Striping Logic and to store the obtained data in the internal registers and then send the data to the scrambler and then get the Bit-by-Bit scrambled data from the Scrambler a
scrambler
- example file Scrambling for DSP application book
yuanchengxu
- 基于Verilog HDL的通信系统设计-Design of communication system based on Verilog HDL
scrambler-wimax
- This package contains synthesizable VHDL codes for scramber/descrambler module for IEEE 802.16 WiMAX PHY layer.
scramble
- 基于VHDL实现加扰器解扰器的设计，与仿真。-VHDL-based scrambler descrambler design and simulation.
ParallelScrablerDescrambler
- VHDL code for parallel 6-bit scrambler and descrambler
scrambler-matlab
- it is scrambler using matlab
scrambler
- Verilog编写的ADC加扰程序（scrambler）里边附有加扰器的说明，实验可以把数据打散，可自行写testbench测试-Verilog prepared by the ADC scrambled program (scrambler) inside with scrambler descr iption, experimental data can be broken up, write their own testbench test
DATA_Scramble
- 扰码器的FPGA实现，选择的扰码器规格为15位移位寄存器。(FPGA scrambler, scrambler specifications for a 15 bit shift register.)
shift&scrambler
- shift &scramble codes and it tb
scrambler
- 通讯领域很多对原始数据进行加饶，加饶的多项式可以有很多种。上面是一种实现，可以参考实现其它加饶的多项式， 同理如果实现解扰可以反过来