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3des_vhdl_latest
- 3DES的VHDL IP核，64位 标准FIPS 46-3 NIST,并且使用3组64位密钥-The VHDL implementation 3DES，The core complies with the Triple-DES 64-bit block cipher defined in FIPS 46-3 NIST standard and operates with three 64-bit keys. Functional Descr
SIMULATION-AND-SYNTHESIS-OF-TRIPLE-DES-BLOCK-CIPH
- SIMULATION AND SYNTHESIS OF TRIPLE-DES BLOCK CIPHER USING VHDL
My_DES3
- a triple-DES (Data Encryption Standard) hardware descr iption in verilog-HDL with testbench
SIMULATION-AND-SYNTHESIS-OF-TRIPLE-DES-BLOCK-CIPH
- This project presents FPGA implementations of the DES and Triple-DES with improved security against power analysis attacks. The proposed designs use Boolean masking, a previously introduced technique to protect smart card implementations from these
DES_Triple-DES-IP-Cores
- Triple DES 密码算法。 利用Xillinx公司的Virtex-II芯片测试了。正常动作。-Triple DES core implementation in verilog. It takes three standard 56 bit keys and 64 bits of data as input and generates a 64 bit encrypted/decrypted result.