搜索资源列表
fifotop
- 基于FPGA编写的VHDL语言，FIFO代码程序。 程序完整。-VHDL-based FPGA written language, FIFO procedure code. Complete the procedure.
gencontrol
- 高速任意波形产生器控制模块 控制NCO,FIFO，并串转换-hign-speed wfgenerator control
ASYNCFIFO
- 异步FIFO的FPGA实现,XILINX FPGA, ISE ,VHDL语言实现-asynchronous fifo
VHDL06
- 16×4bit的FIFO设计代码，学习代码，请在下载24小时后删除。-16 × 4bit the FIFO design code, learning the code, please delete after 24 hours to download.
FIFO
- VHDL code for first in first out register
8fifo
- 可综合的 8x8 fifo VHDL 源代码-Can be integrated 8x8 fifo VHDL source code
fifi
- FIFO code written in VHDL
THS1206
- FPGA来实现数据采集，AD采用TI公司的THS1206，高速并行AD，内含16字FIFO，降低硬件复杂度。-FPGA to realize data acquisition, AD using TI company s THS1206, high-speed parallel AD, containing the 16-character FIFO, to reduce hardware complexity.
fifo
- first in first out VHDL code
caiyang
- 种用FPGA 实现对高速A/ D 转换芯片的控制电路,系统以MAX125 为例,详细介绍了含有FIFO 存储器的A/ D 采样控制电路的设计方法,并给出了A/D 采样控制电路的V HDL 源程序和整个采样存储的顶层电路原理图.-Species with FPGA to achieve high-speed A/D conversion chip control circuit, the system as an example to MAX125 details FIFO memory cont
FIFO
- 一个先入先出FIFO的VHDL实现，程序经过了编译验证。-A FIFO FIFO to achieve the VHDL, verification procedures have been compiled.
yuyincaiji
- 语音采集与回放系统源代码：1.为了使读音数据存储的时间更长，速度更快，选用了256K*16Bit的SRAM；2.为了减少单片机的控制复杂度，使用了FPGA来控制SRAM的读写操作，节约了不少单片机的I/O资源；3.为了以后的高速数据存储，本设计中加入了fifo,其位宽及深度可在程序中自由设置，方便灵活。-Speech acquisition and playback system source code: 1. In order to make pronunciation longer data
Asynchronous_FIFO_v6_1
- 详细介绍了异步FIFO的设计方法,以及fpga的仿真波形-Described in detail the design of asynchronous FIFO method and the simulation waveform fpga
Altera_FIFO
- Altera FIFO的多极级联，实现多个FIFO之间的数据传输。-Altera FIFO multi-polar cascading between multiple FIFO data transmission.
afifo_0916
- 异步FIFO，使用XILINX产品实现，可以通过改参数来重新修改深度和位宽-Asynchronous FIFO, using the XILINX product realization, you can change parameters to re-modify the depth and Width
FIFO
- here is realized simple FIFO stack in vhdl. very simple example, but very helpful.
pgm
- uart vhdl code contains all the neceesary things for a uart of speed 2 mbps and has a fifo of 64 KB
SLAVE_FIFO_16BITS
- 68013和FPGA通信 含有68013 slave firmware 含有FPGA VHDL程序-communication between 68013 and FPGA including 68013 slave firmware including FPGA VHDL code
fifo2
- 异步双时钟fifo，vhdl源代码。基本组成是定制的fifo加上空满判断逻辑，基本功能都有-Asynchronous dual clock fifo, vhdl source code. Fifo basic component is a custom air filled with the logic to judge the basic functions are
sdcard_mass_storage_controller_latest.tar
- 基于wishbone总线的SD Card IP Core,有Verilog和VHDL两种语言版本,包含了FIFO和DMA两种实现方式,是开源的IP Core-Based on the wishbone bus SD Card IP Core, there are two language versions of Verilog and VHDL, including the FIFO and DMA implemented in two ways, is open source IP Core