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memtest
- 在数字系统中,一般存在多个芯片,利用不同的特点用于实现不同的功能,一般都包含CPU,FPGA,AD,DA,memory,ASSP(专用标准模块),ASIC等。CPU用于进行智能控制,FPGA进行硬件算法处理和多设备接口,AD进行模数转换,DA进行数模转换,memory存储临时数据。因此,FPGA如何与其他芯片进行通讯是重要的设计内容。数据输入,数据输出,双向通讯,指令传递,地址管理,不同时钟的异步通讯问题等等都需要处理。最基本的MEMORY如SRAM(128KX8bbit静态存储器628128)
RGB_Control
- 能将24bit的1080i数据直接存储到fifo中,经过实际的板子验证。还可以通过更改参数改到其他格式,如1080P,720P,720I等。-24bit of 1080i can store data directly to the fifo, the board after the actual verification. Can also be changed by changing the parameters to other formats such as 1080P, 720P, 7
RGB_480P
- 用VHDL写的,将24bit的480P数据直接存储到fifo中,经过实际的板子验证。还可以通过更改参数改到其他格式,如1080P,720P,720I等。-Written with VHDL, the 480P 24bit data will be stored directly to the fifo, after the actual board certification. Can also be changed by changing the parameters to other for
FIFOadnVHDL
- FIFO (先进先出队列)是一种在电子系统得到广泛应用的器件,通常用于数据的缓存和用于容纳异步信号的频率或相位的差异。
RamFifoVHDL
- Ram Fifo Core VHDL file
fifo89
- 先进先出FIFO缓冲器,8位字宽,9位字深,很简易的缓冲器。-FIFO FIFO buffer, 8-bit word wide, 9-bit words deep, very simple buffers.
vhdl
- 该系统通过顶层模块,调用7底层模块实现。7大模块底层模块为:理想信源数据接收模块,理想信源数据缓存模块,LAPS成帧模块,加扰并发送LAPS帧模块,接收LAPS帧并解扰模块,接收LAPS帧数据缓存模块,解帧并发送数据给理想信源模块。另,还有一个fifo模块,以便两个缓存模块调用。-The system top-level module, called 7, the bottom module. Bottom-7 module module: the ideal source of data re
fifo
- 利用VHDL实现fifo,IPcode 的 FIFO-vhdl for fifo
sfifo
- 牛逼的娴熟的异步fifo,vhdl程序,波形完美-fifo
FT2232H_USB_Core
- 在FPGA外扩用FT2232 实现UART TO USB 2.0 的通信。-The FT2232H is a USB2.0 Hi-Speed USB Device to FIFO IC. This core allows the use of this chip with an FGPA design in high speed FT245 style synchronous FIFO mode. Data rates up to 25 mbytes/s can be achieve
fifo_chipscope
- 学习FIFO的初级资料,代码工程在ISE10.1上运行,还有在线示波器chipscope的步骤指导哦!-Study of the primary data FIFO, the code works ISE10.1 run, there is scope chipscope step online guide Oh!
FIFO
- 这是用VHDL设计的一个8*9阵列的D触发器组成FIFO(first in first out)-This is a VHDL design using an 8* 9 array of D flip-flop composed of FIFO (first in first out)
FIFO24_CS8416[1]
- Fifo buffer vhdl code
actel_FPGA_example_source
- actel中的FIFO的使用的示例代码,对于使用actel环境的初学者有一定的帮助。-actel the use of FIFO in the sample code for beginners to use actel environment will certainly help.
FIFO
- 用VHDL语言编程实现的FIFO的设计,可用于数据的寄存和缓冲,libero仿真通过-Programming language using the FIFO VHDL design can be used for data storage and buffering, libero simulation by
fifo
- 异步FIFO的VHDL程序,已经通过quartus编译和仿真。 -Asynchronous FIFO, VHDL program, has been compiled by quartus and simulation.
fifo
- fifo in vhdl file code
fifo.vhdl
- 异步fifo的vhdl源代码,可实现异步信号的传送-The asynchronous fifo vhdl source code, enabling the transmission of asynchronous signals
FT245
- 在FPGA实现一个与外围USB FIFO 通信的FIFO控制核-The FPGA to implement a communication with the external USB FIFO FIFO control nuclear
fifo_vhdl
- 基于fpga,cpld的异步FIFO的设计 用VHDL语言进行相关的功能模块设计-Based on fpga, cpld design of asynchronous FIFO associated with VHDL design modules