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A VHDL logical example of memory delay controller -A VHDL logical example of memory delay controller
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sdram_controller_latest.tar.gz -it is memory DDR controller, but it has 8 bit only data bus wide ,and hasn’t independents clock for source read-write data and ddr + controller size. Wrote on the VHDL language.-sdram_controller_latest.tar.gz -it is me
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Intel Strata Flash Memory (P30)接口控制器的VHDL源代码-Intel Strata Flash Memory (P30) interface controller of the VHDL source code
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MIPS CPU with Mulicycle Datapath. This is a custom RISC processor implemented to achieve the function of "lw, sw, add, sub, and, or, beq, j"
Mem.vhd - memory
buffer.vhd - buffer
ALUcon.vhd - Alu controller
pc.vhd - program counter
REG - reg
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Package consists of two pdf files:
i)cdr project: theory and implementation of vhdl
ii)I2C bus controller: xilinx implementation of uC interface on CPLD
Package consists of 7 vhdl files:
string_detector: detects the continuous string of 11
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在VHDL开发环境中,实现单片机的cpu的控制器,从存储器中逐条取指令,并进行译码,通过控制电路,完成各种指令操作-In VHDL development environment, to achieve single-chip controller cpu, one by fetching instructions from memory and decodes the control circuit, complete a variety of instruction
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设计一个模型机,具体设计要求如下:
(1)设计指令系统,要求有取数指令、加法指令、跳转指令、停机指令等
(2)设计指令格式、微指令格式 、微程序 、时序电路 、数据通路,完成cpu的设计。
(3)利用模块化设计,分别设计存储器模块、运算器模块、时序电路模块、微程序控制器模块、显示模块等,最后进行系统的顶层设计,完成复杂模型机的设计与实现测试
(4)根据任务,完成主程序的设计,同时把主程序翻译成目标代码,写入主存,仿真下载测试。(Design a model machine, th
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