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直流电机的verilog hdl 代码
- 直流电机的verilog hdl 代码,适合初学者参考,DC motor verilog hdl code, suitable for beginners reference
基于verilog HDL语言的电子钟
- 基于verilog HDL语言的电子钟,多功能电子时钟,Verilog HDL language-based electronic bell, electronic multi-function clock
SPIsend.rar
- Verilog HDL的程式,上網找到SPI程式, vspi.v這程式相當好用可用來接收與傳送SPI,並且寫了一個傳輸信號測試,spidatasent.v這程式就是傳送的資料,分別為00 66... 01 77...... 02 55這樣的資料,並透過MAX+PULS II軟體進行模擬,而最外層的程式是test_createspi.v!,Verilog HDL programs, Internet find SPI program, vspi.v this very useful progra
lab.rar
- verilog hdl经典例程,全部调试通过,verilogHdl example,all can be used
EPM240_SCH_and_program.rar
- EPM240 cpld 原理图+程序。 Verilog HDL语言。 程序有正弦波发生器,ADC0804直流采样和显示,汉字滚动,交通灯,键盘,显示程序,计数器等等。,Schematic diagram+ EPM240 cpld procedures. Sine wave generator procedures, ADC0804 DC sampling and showed that Chinese scroll, traffic lights, keyboard, display pro
DDS
- 我们小组共了一个月做的DDS,程序核心用的是Verilog HDL,有仿真波形,输出正弦波,方波,及三角波,步进可调.频率范围1HZ--10MHZ-Our group for a month to do a total of DDS, the procedure is used in the core of Verilog HDL, there are simulation waveform, the output sine wave, square wave and triangular wa
iir
- 基于verilog HDL的IIR数字滤波器的实现-Verilog HDL-based implementation of the IIR digital filter
ping_pong_buffer
- 用寄存器来实现乒乓缓存(Verilog HDL)-Ping-pong with the register to achieve cache (Verilog HDL)
mcst
- 曼彻斯特编码实现,verilog HDL 做的,我也是从网上下的-Manchester encoding to achieve, verilog HDL to do, I am also from the Internet under
multiply
- Verilog hdl语言 常用乘法器设计,可使用modelsim进行仿真-Verilog hdl language commonly used multiplier design, can use the ModelSim simulation
1602
- verilog HDL语言编写的完整工程,功能是点亮1602lcd,在lcd上显示英文和数字-verilog HDL languages complete works, the functions of light 1602lcd, in the lcd display in English and the number of
Verilog-SRAM
- 用verilog hdl语言编写的fpga与片外sram 的读写控制-With the verilog hdl language fpga sram chip with read and write control
spi_verilog
- SPI协议Verilog HDL程序,内含testbench 文件
verilog
- 基于Verilog HDL的通信系统设计一书的电子教案,里面有很多例子,大家可以参考一下-Verilog HDL-based communication system design e-book lesson plans, there are many examples we can refer to
Verilog.HDL.Experiment
- Verilog.HDL.Experiment.例程-Verilog.HDL.Experiment. Routine
source3-6
- verilog hdl教程135例:verilog hdl语言类似于C语言,便于学习。本文档带有源代码,3-6章-Verilog HDL 135 cases Guide : Verilog HDL language similar to the C language, to facilitate learning. This document with the source code, 3-6
VerilogHDL
- verilog hdl 综合实用教程,一本非常实用易学易懂的书-verilog hdl Comprehensive practical tutorial, a very useful book to learn to understand
shuzizhong
- 设计一个能进行时、分、秒计时的十二小时制或二十四小时制的数字钟,并具有定时与闹钟功能,能在设定的时间发出闹铃音,能非常方便地对小时、分钟和秒进行手动调节以校准时间,每逢整点,产生报时音报时。 实验平台: 1. 一台PC机; 2. MAX+PLUSII10.1。 Verilog HDL语言实现,还有完整的实验报告-The design of a can be hours, minutes, seconds time of 12 hours or 24 hours system, d
4weishuzipinlvjikongzhimokuai
- Verilog HDL下的4 位数字频率计控制模块源代码-Verilog HDL under four digital frequency meter control module source code
Verilog_HDL
- Verilog HDL程序设计教程,以可综合的设计为重点,同时对仿真和模拟也作了深入阐述。全面介绍了verilog HdL 词法,语法。-Verilog HDL Programming Guide, to be designed as an integrated focus on simulation and simulation at the same time also made to describe further. Verilog HdL gave a comprehensive ac