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ad9777的测试程序，对SPI进行初始化，运用ISE环境，成功地进行综合和实现.rar
- ad9777的测试程序，对SPI进行初始化，运用ISE环境，成功地进行综合和实现
spi slave
- SPI 接口的VHDL和Verilog实现。slave模式
mcu-cpld-spi.mcu与cpld之间spi接口程序
- mcu与cpld之间spi接口程序，mcu为master，cpld用verilog写成slave模块,mcu with spi interface program between the CPLD, mcu for the master, cpld written using Verilog slave module
SPI_AT45DB041B.rar
- 用verilog编写的SPI程序,SPI芯片是AT45DB041B.文件内包含程序仿真时的截图.包括read和wirte.,SPI prepared using Verilog procedures, SPI chip AT45DB041B. Document contains procedures for simulation screenshot. Including read and wirte.
SPIsend.rar
- Verilog HDL的程式，上網找到SPI程式， vspi.v這程式相當好用可用來接收與傳送SPI，並且寫了一個傳輸信號測試，spidatasent.v這程式就是傳送的資料，分別為00 66... 01 77...... 02 55這樣的資料，並透過MAX+PULS II軟體進行模擬，而最外層的程式是test_createspi.v！,Verilog HDL programs, Internet find SPI program, vspi.v this very useful progra
SPI_Wishbone_Controller
- FPGA SPI总线硬件描述语言Verilog下的实现-FPGA SPI bus under the Verilog hardware descr iption language to achieve
spi
- SPI总线接口的verilog源码，包含仿真模块modelsim 和 quartus 工程。本人测试通过。-SPI bus interface in verilog source code, including the simulation module modelsim and quartus project. I test.
SPI
- 基于FPGA的SPI控制器的设计，有代码和相关文档资料-the design of SPI controlor ,including verilog codes and other documents
SPI
- Verilog SPI 源码（来自网络）-Verilog SPI
spi
- Verilog语言写的SPI接口（层次化设计，便于升级）-The implememt of SPI interface using Verilog HDL
SPI_FireWall
- verilog spi file with testbench
spi
- SPI Verilog code with programmable clock
spi
- SPI IP CORE Verilog quartus-SPI IP CORE Verilog quartusii
modelsim
- verilog SPI master 的完整实验报告 仅供参考 切勿抄袭-verilog SPI master
spi
- this the SPI slave module -this is the SPI slave module
verilog-SPI-core
- 用VerilogHDL写的spi 核的例子-A simple example of SPI core using Verilog HDL
Nitro-Parts-lib-SPI-master
- Nitro-Parts-lib-SPI Verilog SPI master and slave
FPGA与SPI接口程序(hdl源代码)
- FPGA,VERILOG,SPI串口通信；(FPGA,VERILOG,SPI;;;;;;;;;)
spi
- 实现spi写功能，读功能，仿真，板级调试都通过验证了。(achieve write function and read function of spi, simulation is verified)
spi final
- verilog 实现spi 串口 通过FPGA板可以看出数据传输(verilog spi can be demonstrated with FPGA)