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sha-1.rar
- 本算法基于leon2协处理器接口标准，内含testbench，在modelsim中仿真通过，在ise9.2中综合及后仿真通过。,The algorithm is based on the leon2 co-processor interface standard, including testbench, ModelSim simulation in the adoption, in ise9.2 integrated and adopted after the simulation.
PWM
- 使用VERILOG 语言产生PWM波。只需要使用处理器或内核直接配置相应的寄存器就可以输出PWM波。-VERILOG language use PWM wave generated. Only need to use the processor or core directly corresponding configuration register can output PWM wave.
FPGA_FFT
- 基于FPGA的高速FFT处理器的设计与实现-FPGA-based high-speed FFT Processor Design and Implementation
alu
- verilog code for alu in RISC processor
verilog_design_a_simple_cpu
- 用verilog设计一个简单的cpu系统-Verilog design with a simple cpu system
mips_multi
- mips processor multicycle non-pipelined microprocessor by verilog
webCam-FPGA
- 使用Verilog控制美光CMOS图像处理器，并转存到SDRAM中。使用FPGA为QL的带fuse系列-Control the use of Verilog Micron CMOS image processor and SDRAM in转存到. FPGA for use with QL series fuse
mmarm_EDACN
- 用FPGA实现ARM嵌入式处理器功能的Verilog源码及说明-FPGA with embedded ARM processor to achieve the functional descr iption of Verilog source code and
TrackingPresentation_jon
- presentation a low cost video tracking algorithm implemented on an Altera DE2 board with Cyclone II processor. System uses a VGA controller and several SG-DMA s-presentation on a low cost video tracking algorithm implemented on an Altera DE2 board wi
mips
- 使用verilog設計的MIPS處理器，mips處理機的模擬且可合成驗証-MIPS processor using the verilog design, mips processor synthesis of analog and can be verified
SDR
- FPGA based implementation of a SDR - codes in Verilog HDL for the processor and control.-FPGA based implementation of a SDR- codes in Verilog HDL for the processor and control.
mlite.tar
- 很强大的mips处理器，用verilog实现的-A very strong mips processor implemented using verilog
m1_core.tar
- 一个小巧的mips处理器，verilog写的，大家可以-A small mips processor, verilog written, we can see
processor
- verilog program for alu
Processor_alu
- this Code is in verilog HDL. This Code is for piplined processor with 4 opcode. this will work in three cycle latch, decode and exicute.. test bench for xilinx ise is laos given
SinglecycleCPU
- 用Verilog实现一个简单的单周期CPU，并运行Quicksort程序以验证正确性。-This file is written in Verilog to achieve a single cycle processor. It can run in Quartus2.
Superscalar_processor_verilog
- super scalar Processor implemented in Verilog. Details about project included.-super scalar Processor implemented in Verilog. Details about project included.
mips
- in verilog 8bit mips processor
grlib-tmtc-1.0.18.tar
- Zipped LEON3 processor VHDL core.
ARM-Verilog-HDL-IP-CORE
- ARM处理器的IP核，用verilog编写的，对处理器和相关的CPU架构知识有很大帮助。-ARM processor IP core, written in verilog processor and CPU architecture knowledge.