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sva_assetion
- 学习SVA的最基本的例子，对于想了解systemverilog assertion的相关人员非常有用！-SVA learn the most basic example, the systemverilog assertion would like to know the person very useful!
SystemVerilogEventRegionsRaceAvoidanceGuidelines.r
- The IEEE1800 SystemVerilog Standard includes new event regions primarily added to reduce race conditions between verification code and SystemVerilog designs. The new regions also facilitate race-free Assertion Based Verification (ABV). This pap
Constraint-Based-Verification
- 系統化驗証方法及實例探討Assertion, Constraint synthesis-Electronic Design complexity getting higher, the verification work needs to be fully understood
SystemVerilogAssertion
- SystemVerilog Assertion的应用例子。例子均在Synopsys VCS环境下编译通过。-The uploaded files are examples of Systemverilog Assertions. All of the codes are compiled successfully in Synopsys VCS environment.
assertion_interface_classes
- Assertion and Interface Classes Examples in System Verilog.
Ms32pci
- PCI-ip硬件描述语言-开源的，可以做参考设计，如果需要的话，-This models are written in VHDL! Author is Ovidiu Lupas! MASTER model generates PCI compliant signals checks Target signal compliance with PCI checks data received from Target for correctness generates
SVA-script
- 一个自己总结的systemverilog assertion读书笔记，基本上systemverilog assertion的语法比较全。简单易懂。适合SVA入门。-systemverilog assertion scr ipt
DigitalDesignofSignalProcessing
- This chapter begins from the assertion that the advent of VLSI (very large scale integration) has enabled solutions to intractable engineering problems.
std_ovl_v2p7_Feb2013
- 目前最新的OVL库，里面是标准的ASSERTION模块，支持VHDL刚Verilog，最近在做AXI协议验证的时候用到，分享下-The latest OVL(open verification library),including all standard module of assertions(VHDL and Verilog). It can be used into AXI Protocl Verification. Just share with you guys.
SystemVerilog-Assertions-source-code
- SystemVerilog Assertion 应用指南一书的每章断言源代码，很好的SVA学习资料-SystemVerilog Assertion Application Guide for each chapter of a book asserts the source code, a very good learning materials SVA
Day-1-Training-Material
- OneSpin培训资料 OneSpin用于做断言验证。-OneSpin training material is used to study assertion verification in ASIC design.
Day-2-Training-Material
- OneSpin培训资料 ASIC设计领域，OneSpin用于做断言验证。-OneSpin training material can help user study assertion verification method in ASIC design.
Day-3-Training-Material
- OneSpin培训资料 OneSpin广泛用于芯片设计的断言验证。-OneSpin training material can help user understand how to do assertion verification in ASIC design.
wb_uart_latest.tar
- 实现一个一16750/16550 UART。该UART内核是完全基于另一个OpenCores的项目：UART_16750塞巴斯蒂安维特。 请找到有关于UART内核的文档。 该接口是现在有8位Wishbone总线兼容。 随着GHDL模拟器只需运行： ./ghdl_uart.bat 使用任何其他模拟器，开始模拟以下perl脚本必须运行之前： uart_test_stim.pl> FILENAME.TXT 其中，FILENAME.TXT是通用的“stim_
SystemVerilog断言及其应用
- 该书用来阐述如何使用断言，以及断言的语法和示例(The book is devoted to the use of assertions, as well as to the syntax and examples of assertions)
systemverilog+assertions应用指南
- system verilog assertion介绍(system verilog assertion introduction)