搜索资源列表
SystemVerilogAssertions
- Srikanth Vijayaraghavan - A Practical Guide for SystemVerilog Assertions-Srikanth Vijayaraghavan- A Practical Guide for SystemVerilog Assertions
Advanced_Electronic_Design_with_VHDL
- One of these files is a design automation guideline with advanced VHDL samples. The material can be used either by beginners as well as by experienced digital designers. The second file teaches how to use PSL assertions in VHDL designs.
SystemVerilogAssertion
- SystemVerilog Assertion的应用例子。例子均在Synopsys VCS环境下编译通过。-The uploaded files are examples of Systemverilog Assertions. All of the codes are compiled successfully in Synopsys VCS environment.
sva
- sva断言，Assertions on overlapping behaviour with SVA-Assertions on overlapping behaviour with SV
std_ovl_v2p7_Feb2013
- 目前最新的OVL库，里面是标准的ASSERTION模块，支持VHDL刚Verilog，最近在做AXI协议验证的时候用到，分享下-The latest OVL(open verification library),including all standard module of assertions(VHDL and Verilog). It can be used into AXI Protocl Verification. Just share with you guys.
SystemVerilog-Assertions-source-code
- SystemVerilog Assertion 应用指南一书的每章断言源代码，很好的SVA学习资料-SystemVerilog Assertion Application Guide for each chapter of a book asserts the source code, a very good learning materials SVA
SystemVerilog断言及其应用
- 该书用来阐述如何使用断言，以及断言的语法和示例(The book is devoted to the use of assertions, as well as to the syntax and examples of assertions)
systemverilog+assertions应用指南
- system verilog assertion介绍(system verilog assertion introduction)