搜索资源列表
BOSCH_CAN_V20_en
- The acceptance and introduction of serial communication to more and more applications has led to requirements that the assignment of message identifiers to communication functions be standardized for certain applications. These applications can
1.报警系统程序
- 用C编程实现的一个单片机报警系统！已经调试可以使用！是单片机大作业的一个！--A SCM alarm system. It is written in C language. It is a part of a big assignment on SCM.
AssignmentP3
- Assignment 3 Construct VHDL models for 74-139 dual 2-to-4-line decoders using three descr iption styles, i.e., behavioral, dataflow and structural descr iptions. (1) Synthesize and (2) simulate these models respectively in the environment of Xilinx
Assignment
- DSP课程的作业，显示低通巴特沃斯滤波器的滤波效果。代码和仿真图已经给出。-DSP course work, low-pass Butterworth filter shows the filter effect. Code and simulation map has been given.
Verilog--shiyanbaogao
- 有实验结果,用MOSIN6编写的,是Verilog HDL语言实现的. 练习三 利用条件语句实现计数分频时序电路 实验目的： 1. 掌握条件语句在简单时序模块设计中的使用； 2. 学习在Verilog模块中应用计数器； 3. 学习测试模块的编写、综合和不同层次的仿真。 练习四 阻塞赋值与非阻塞赋值的区别 实验目的： 1． 通过实验，掌握阻塞赋值与非阻塞赋值的概念和区别； 2． 了解阻塞赋值与非阻塞赋值的不同使用场合； 3． 学习测试模块的编写、综合和不同层
logicassign
- 同一基类型的两分辨类型的赋值相容问题,各个源描述的编译顺序是:logic.vhd,assign.vhd-The same base type to distinguish the two types of assignment compatibility issues, the various sources described in the order of the compiler: logic.vhd, assign.vhd
wervhdl
- 赋值语句有两种，即信号赋值语句和变量赋值语句。每一种赋值语句都有三个基本组成部分，即赋值目标、赋值符号和赋值源。信号赋值语句和变量赋值语句的语法格式如下 :-There are two assignment statements, that is, the signal assignment statements and variable assignments. Each assignment has three basic components of the assignment objec
SpiralMatrix1
- 螺旋矩阵算法编程，沿各个矩形边框依次给矩阵的每一个元素赋值，在计算机内存中构造一个完整的螺旋矩阵，然后输出。-Spiral Matrix Algorithm for programming, along the border each rectangle in turn give the matrix elements of each assignment, in the computer memory to construct a complete spiral matrix, then ou
MyClickExample
- simple click. you can use this to complete your assignment
BEIHANGVerilogjiaocheng
- 北航Verilog教程. Verilog HDL基本结构 数据类型及常量、变量 运算符及表达式 语句 赋值语句和块语句 条件语句 ... -BUAA Verilog Tutorial. Verilog HDL data types and the basic structure of constants, variables and expression operator assignment statements and conditional stat
7279
- 采用7279显示模块，应用六个按键控制六个数码管的显示，还可以调用其他赋值函数个智能小车副占空比。-Using 7279 display module application of the six keys to control the display of six digits, you can call the other assignment functions of the smart car, deputy duty cycle
52
- Verilog HDL中关于赋值语句的ppt-ppt on Verilog HDL assignment statements
QuadD
- 四路D型触发器 这个例子表明一个条件任务状态能够怎样被使用来描述连续的逻辑-Quad D-Type Flip-flop This example shows how a conditional signal assignment statement could be used to describe sequential logic
ASSIGNMENT_1
- its an assignment given to us on 2 way traffic controller
assignment
- this a n assignment in my class VLSI design-this as an assignment in my class VLSI design
Ejercicio_5
- SSD4. Exercise 5. This assignment is to create an interface for entering a time zone.
Assignment-CNF(ADSA)
- advance data structure assignment
Assignment-3
- assembly 语言作业 电梯-assembly language assignment- elevator
assignment-1
- verilog coding assignment for basic programs
FPGA-pin-assignment
- FPGA管脚分配需要考虑的因素，经验之谈，有很强实用价值-it is about The FPGA pin assignment