搜索资源列表
chap12
- 《Verilog HDL 程序设计教程》9-"Verilog HDL Design Guide" 9
chap12
- 16个常用HDL编码打包上传 包括记数器，多路选择器，全加/半加器等，均通过modsim验证-16 commonly used HDL coding package upload includes counter, MUX, all add/semi-add, etc., are adopted to verify modsim
chap3
- Verilog源代码一共135例chap3-chap12，初学必备-Verilog source code for a total of 135 cases of chap3-chap12, beginner necessary
chap5
- Verilog135例，chap3-chap12,初学必备-Verilog135 cases, chap3-chap12, beginner necessary
chap6
- Verilog135例，chap3-chap12,初学必备-Verilog135 cases, chap3-chap12, beginner necessary
chap7
- Verilog135例，chap3-chap12,初学必备-Verilog135 cases, chap3-chap12, beginner necessary
chap12
- 本程序是关于学习VERILOG语言的案例，方便读者快速掌握VERILOG语言的基本语法，操作等-This program is about learning the language of the case VERILOG to allow readers to quickly master the basic syntax of the language VERILOG, operation, etc.
chap12
- 16个常用HDL编码打包上传 包括记数器，多路选择器，全加/半加器等，均通过modsim验证-16 commonly used HDL coding package upload includes counter, MUX, all add/semi-add, etc., are adopted to verify modsim
chap12
- 16个常用HDL编码打包上传 包括记数器，多路选择器，全加/半加器等，均通过modsim验证-16 commonly used HDL coding package upload includes counter, MUX, all add/semi-add, etc., are adopted to verify modsim