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单片机应用系统设计与产品开发的光盘（作者冯建华）
本代码包含了第4章～第10章案例的源程序和电路布线图（Protel布线），分别存放在每一章相应目录（如，第4章对应目录“第4章”）下的“\源代码”和“\电路图”两个子目录中。源程序可利用普通的文本编辑工具打开、查看；电路图应利用Protel（笔者建议）打开、查看。
第9章与第8章的电路图完全相同，本章目录中只有源程序，没有电路图。
读者在编译和处理源程序、电路图的时候，尽量将他们复制到一个专门的磁盘目录中，并注意实时保存中间结果
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Verilog source code is usually typed into one or more text files on a
computer. Those text files are then submitted to a Verilog compiler
or interpreter which builds the data files necessary for simulation or
synthesis. Sometimes simulation imm
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0下载：
Verilog source code is usually typed into one or more text files on a
computer. Those text files are then submitted to a Verilog compiler
or interpreter which builds the data files necessary for simulation or
synthesis. Sometimes simulation imm
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0下载：
Verilog source code is usually typed into one or more text files on a
computer. Those text files are then submitted to a Verilog compiler
or interpreter which builds the data files necessary for simulation or
synthesis. Sometimes simulation imm
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0下载：
Verilog source code is usually typed into one or more text files on a
computer. Those text files are then submitted to a Verilog compiler
or interpreter which builds the data files necessary for simulation or
synthesis. Sometimes simulation imm
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