Generate trellis data of a rate-1/n convolutional encoder.卷积码1/n的编码器，注意生成的是非系统码。-Generate trellis data of a rate-1/n convolutional encoder. Convolutional codes 1/n of the encoder, the attention generated by the non-system code.

本设计是一个基于FPGA的咬尾卷积码编码器设计，要求使用verilog语言编写编码器模块，通过编译和综合，并通过matlab和modelsim仿真对比验证设计结果。-The design is an FPGA-based tail-biting convolutional code encoder design requires the use verilog language encoder module, through compilation and synthesis, and by c

This a convolutional encoder in xilinx virtex-5 ML506 board FPGA. This program use matlab for comunicating with FPGA. The convolutional encoder using rate 1/2, and 1/3.The register are 3,4,5,6 and 7.-This is a convolutional encoder in xilinx virtex-5