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8051 Counter 0 Example Program
- 8051单片机的计数器0的操作程序源代码-8051 0 counter the source code for the procedure
counter&adder
- counter and adder program by vhdl. Just enjoy it!-counter and adder program by VHDL. Just enj oy it!
MCU-counter
- 用verilog实现单片机计数器 用verilog实现单片机计数器-MCU with verilog counter with MCU counter verilog
Verilog 编写的 计数器
- 用 verilog 编写的updown counter
people-counter.rar
- 基于16f877的单片机人数统计系统源码，可统计进出门的人数，用数码管显示,16f877 microcontroller based on the number of source statistical system can go out into the number of statistics, with digital display
C51-counter.rar
- 用C51座位CPU的计算器，具备8位数加减乘除功能。P0作为数码管的段控制，P2作为数码管位显示控制，P3控制4x4键盘阵列。,C51 as the CPU, the counter can process 8 bit numbers "+,-,*,/". P0 contro the LED and P2 for which bit,P3 oprate the keyborad
counter.rar
- 初学者学习modelsim的好例子，基于Verilog的计数器，带测试源码，在quartus2运行。,Modelsim beginners to learn a good example of Verilog based on the counter, with the test source code, running in quartus2.
c8051f330
- 基于C8051F330的正弦波、PWM、计数器、频率测试等功能实现-C8051F330 based on the sine wave, PWM, counter, frequency of testing functions
counter
- 关于FPGA实现的几种计数器的verilog源程序-FPGA implementation of several counter verilog source code
counter
- 6位数显频率计数器的proteus仿真电路及C语言程序设计，单片机仿真实例-6-digit frequency counter of proteus was circuit simulation and C language programming, microcontroller simulation
counter
- 计数器,显示结果在4个数码管上。！~！ 计数器,显示结果在4个数码管上。！~！-COUNTER
counter
- 适用于FPGA Xilinx开发板的Counter程序，计数从0到9999，在板上用4位7段数码管显示，可实现双向计数。-Applicable to FPGA Xilinx development board of the Counter procedures, counting from 0 to 9999, in the board with four 7 digital display, enabling two-way counts.
frequency-counter-pic
- C51 designed using the frequency counter, it will automatically switch range, there are testing the data source
counter
- 用verilog写的计数器，可用于分频等多种功能。已经调试成功很好用-Written with verilog counter, can be used for frequency and other functions. Has been very good success with debugging
counter
- 用VHDL语言编写COUNTER-FPGA VHDL COUNTER
counter
- -- Mod-16 Counter using JK Flip-flops -- Structural descr iption of a 4-bit binary counter. -- The first two design entities describe a JK flip-flop and a 2-input AND gate respectively. -- These are then packaged together along with a signal
led on off-waiting counter
- led on off with waiting counter
counter
- Counter example for FPGA with VHDL
counter
- counter by implementation vhdl
bcd counter
- Binary counter design in verilog