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用Verilog HDL语言实现FPGA的频率等精度测量。（已经过验证）-Using Verilog HDL language, such as FPGA frequency measurement accuracy. (Has already been verified)
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verilog写的频率计程序的计数模块,-Verilog written procedures for counting frequency meter module,
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有实验结果,用MOSIN6编写的,是Verilog HDL语言实现的.
练习三 利用条件语句实现计数分频时序电路
实验目的：
1. 掌握条件语句在简单时序模块设计中的使用；
2. 学习在Verilog模块中应用计数器；
3. 学习测试模块的编写、综合和不同层次的仿真。
练习四 阻塞赋值与非阻塞赋值的区别
实验目的：
1． 通过实验，掌握阻塞赋值与非阻塞赋值的概念和区别；
2． 了解阻塞赋值与非阻塞赋值的不同使用场合；
3． 学习测试模块的编写、综合和不同层
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是用verilog写得加法器以及计数器里面有测试文件（testbench），对于初学者来说这个可以用来参考下-Is written in Verilog adder and counter inside a test file (testbench), for beginners this can be used to reference the next
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an up down counter in verilog
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It is a simple 4-digit bcd up down counter written in verilog
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利用Verilog实现的数字钟和汽车尾灯，有闹钟，报时，置数等多种功能-Verilog
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Verilog 编写的频率计，使用8位LED作为显示，Quartus II 6.0的工程文件。保证好用，EPM240T的芯片。使用了66 的资源。-Written in Verilog frequency counter, using 8-bit LED as the display, Quartus II 6.0 of the project file. To ensure easy to use, EPM240T chips. 66 of the resources used.
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synchronous counter in verilog
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计数器Verilog源程序，可轻易实现数目的计算，包含源程序及实现方法。-Counter Verilog source code, the number of calculations can be easily achieved, including source code, and Realization.
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clock divider for fpga in verilog and vhdl
it contains
counter.vhd
clock1.v
clock_divider.doc-clock divider for fpga in verilog and vhdl
it contains
counter.vhd
clock1.v
clock_divider.doc
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Two simple Quadrature decoder and Counter build in a XILINX XC9536 CPLD. This Core is coded in Verilog and contains the compete Project file and the fitted quad.jed File.
The Pinout is descr ipted in the Constrained file quad.ucf.
To use them, y
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用verilog写的计数器，可用于分频等多种功能。已经调试成功很好用-Written with verilog counter, can be used for frequency and other functions. Has been very good success with debugging
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数字频率计
采用Verilog语言编写，分为8个模块，分别是计数器，门控，分频，寄存器，多路选择，动态位选择，BCD译码模块-Digital frequency meter using Verilog language, divided into eight modules, namely, the counter, gated, frequency, register, multiplexer, Dynamic Choice, BCD decoding module
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A Simple Register Counter in verilog Code with 8 bits
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this is a code for mod-6 asynchronous counter in verilog.
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COUNTER DESIGN IN VERILOG
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基于verilog HDL编写的各种实例。。里面记载了计数器，全加器，等等的代码。-Based on various examples written in verilog HDL. . Recording the counter, full adder, and so the code.
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Simple counter in verilog
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Binary counter design in verilog
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