搜索资源列表
risc cpu
- 一个很好的16位cpu ip内核，用quartus写的
8bit Cpu designing
- CPU具有的功能：能完成一些简单的指令 MOV AX,ADDRESS4 --将address4中的内容赋给AX寄存器（在8086/8088汇编语言中称这种寻址方式为直接寻址方式） ADD AX,ADDRESS4 -- 将address4中的内容加到AX寄存器中 SUB AX,ADDRESS4 -- 用address4中的内容减去AX寄存器中的内容 OUT -- 输出AX寄存器中的内容 HLT
CPUCOS.CPU卡操作源程序
- CPU卡操作源程序，对CPU卡及ESAM安全模块具有很好的参考价值,CPU card operated source code, the CPU card and ESAM security module has a very good reference value for
VSCPU.zip 熟悉非常简单CPU模拟器
- 熟悉非常简单CPU模拟器 1、将所给模拟器的源程序编译成执行程序。 2、运行并观察非常简单CPU模拟器, The familiar extremely simple CPU simulator 1, will give the simulator the source program to translate the executive routine. 2nd, movement and observation extremely simple CPU simulator
使用verilog hdl实现16位的cpu设计
- 实现16位的cpu设计 内容使用verilog hdl实现，具体的实现步骤方法，都已经写到文档里面去了！,To achieve 16-bit design of the contents of the cpu using verilog hdl achieve, the specific methods to achieve these steps have already been written inside the document went to!
CPU
- verilog编写CPU： 1. 哈佛存储器结构，大端格式； 2. 类MIPS精简指令集，支持子程序调用和软中断； 3. 实现了乘除法； 4. 五级流水线，工作频率可达80MHz（每个时钟周期一条指令，不计流水线冲突）。 -MIPS like CPU using verilog
CPU
- 用VHDL编的简易16位和8位CPU，可完成加减乘法移位等功能，拥有源码和设计文档，资料齐全-Compiled with VHDL simple 16-bit and 8-bit CPU, to be completed by addition and subtraction multiplication shift functions, with source code and design documents, data and complete
VxWorks-CPU-usage
- VxWorks下如何统计CPU的利用率，VxWorks的SpyLib组件已经部分实现了该功能-How to VxWorks CPU utilization statistics, VxWorks components of SpyLib the function has been partially achieved
CPU
- 八位简单risc cpu 设计的源代码，VHDL语言写的-8 Simple risc cpu design source code, VHDL language written
CPU
- 一个多周期CPU的完整设计，quartus平台，Verilog实现，内含实验报告，和详细的各模块功能表-Complete a multi-cycle CPU design, quartus platform, Verilog implementation, includes lab reports, and a detailed menu of each module
cpu
- verilog编写的简单的CPU，用于参考，已经过仿真-verilog prepared by a simple CPU, for reference, has been simulation
cpu
- 5 stage pipeline CPU, verilog HDL code-5 stage pipeline CPU
CPU
- 16位简单cpu用VHDL语言实现。里面有好几个的》-16-bit cpu with a simple VHDL language. There are several of the "
CPU
- 32位5级流水线CPU设计指令系统、指令格式、寻址方式、寄存器结构、数据表示方式、存储器系统、运算器、控制器和流水线结构等-32bit pipeline CPU
cpu
- 关于FPGA的CPU的设计，可以看一下，大家讨论学习一下啊-The CPU on the FPGA design, you can see, we discussed learning about ah
CPU
- CPU 设计，不错的哦，顶一下哈，希望大家都弄成免费的-CPU design, good Oh, the top click Kazakhstan, I hope we all have to face free
cpu
- cpu的vhdl设计实现加法减法乘法运算-cpu VHDL Design and Implementation of multiplication addition subtraction
cpu
- 16位元浮点数CPU,可作运算,以VHDL编写-16-bit floating point CPU, can be used for computing in order to prepare VHDL
cpu
- 用VHDL语言设计简单的CPU，重点设计微操作代码，然后设计CPU各组成模块，最后根据设计的微操作设计微指令，验证设计的正确性。可基本实现加、减、乘、除、移位、循环等操作。-VHDL language is designed to be simple to use the CPU, the focus of the design of micro-operation code, and then design the components of CPU module designed the f
cpu-16-vhdl
- 用vhdl语用实现简单的16位cpu功能-Pragmatic use vhdl simple function of 16-bit cpu