搜索资源列表
卷积码、CRC
- 卷积码的C源程序，包括编码器和译码器。 还有一个是循环荣誉校验的vhdl]源码。-convolution of C source code, including the encoder and decoder. There is a cycle of the calibration honor VHDL] source.
CRC_VHDL
- 可配置CRC参考设计 xilinx的ip，参考设计文档CRC_xapp562[1].pdf，VHDL语言编写的代码，包含仿真所需文件-configurable CRC Reference Design xilinx the ip, CRC_xapp562 reference design document [1]. pdf, prepared by the VHDL code The simulation includes the necessary documents
ethernet.tar
- 以太网的vhdl和verilog代码，供大家学习-Ethernet VHDL and Verilog code for everyone to learn
crc_8
- 用vhdl编写的CRC校验代码，仿真以及下载在板上测试通过-Prepared by the CRC checksum vhdl code, simulation, and download the on-board test
crc
- CRC-16 VHDL Source Code
crc
- crc32的 vhdl实现源代码，对crc原理有说明-crc32 to achieve the vhdl source code, has made it clear that the principle of the crc
crcvhdl
- crc-vhdl冗余码的vhdl源码，这是16位的crc-crc-vhdl vhdl source code redundancy, which is 16-bit crc
PCK_CRC16_D1
- CRC源代码，VHDL文件，可供参考，16位的-CRC source code, VHDL files, for reference, 16-bit
crc-gen
- CRC Generator is a command-line application that generates Verilog or VHDL code for CRC of any data width between 1 and 1024 and polynomial width between 1 and 1024. The code is written in C and is cross-platform compatible
communications_1
- 用vhdl代码描述的通信系统仿真程序。包括信源（20位m序列），crc编码（采用串行算法），加噪（用22位m序列产生稀疏的1，然后和编码后的数据异或）。-Vhdl code with the simulation program described in the communication system. Including the source (20 m sequence), crc code (using the serial algorithm), noise (with 22 m se
communications_2
- 用vhdl代码描述的通信系统仿真程序。包括信源（20位m序列），crc编码（采用串行算法），加噪（用22位m序列产生稀疏的1，然后和编码后的数据异或），crc解码，数据串行输出。 -Vhdl code with the simulation program described in the communication system. Including the source (20 m sequence), crc code (using the serial algorithm), no
CRC
- CRC循环校验码的生成。文件里是（40，32）的校验码生成电路，采用串行输入、串行输出的方式。-CRC checksum generation cycle. File is (40,32) of the check code generation circuit, the use of serial input, serial output mode.
CRCDecoding
- CRC检错程序。只能检错不能纠错。（40,32）的分组码检错，反馈函数：x8+x7+x4+x3+x+1-CRC error detection process. Not only error detection correction. (40,32) and block code error detection, feedback function: x8+ x7+ x4+ x3+ x+1
crc
- 基于VHDL的CRC编码器的CRC的生成模块源码。-The CRC based on VHDL CRC encoder source code generation module.
CRC
- 对26比特的帧结构进行6比特的CRC处理，输出26+6=32的帧结构。VHDL代码实现-26 bits of the frame structure of 6-bit CRC processing, output 26+6 = 32 frame structure. VHDL code
crc
- 本代码是CRC循环冗余校验实例，包含顶层原理图文件，十分直观-The CRC is cyclic redundancy check code examples, including the top-level schematic file, very intuitive
CRC-8
- VHDL code for CRC-8 computing using 32 bit input (parallel)
CRC
- 赛灵思的循环冗余校验（CRC），内服详细说明-The Cyclic Redundancy Check (CRC) is a checksum technique for testing data reliability and correctness. This application note shows how to implement Configurable CRC Modules with LocalLink interfaces. Users tailor the modul
crc16
- 一个实现CRC16的VHDL代码，以及说明CRC计算的原理和方法。(a VHDL code for CRC16.)
P12_CRC
- VHDL code for CRC algorithm