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primetime
- 这是ＶＨＤＬ语言编写的延时测试程序，用来测定ＣＰＬＤ的性能指标-This is the VHDL language delay the test procedure used to determine the performance CPLD
DDR_SDRAM_controller
- DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides t
bianmakaiguan
- 本代码为编码开关代码，编码开关也就是数字音响中的 360度旋转的数字音量以及显示器上用的（单键飞梭开 关）等类似鼠标滚轮的手动计数输入设备。 我使用的编码开关为5个引脚的，其中2个引脚为按下 转轮开关（也就相当于鼠标中键）。另外3个引脚用来 检测旋转方向以及旋转步数的检测端。引脚分别为a,b,c b接地a，c分别接到P2.0和P2.1口并分别接两个10K上拉 电阻，并且a，c需要分别对地接一个104的电容，否则 因为编码开关的触点抖动会引起轻微误动
crossnoise-R5
- In recent years, due to rapid advances in VLSI manufacturing technology capable of packing more and more devices and wires on a chip, crosstalk has emerged as a serious problem affecting circuit reliability. Even though FPGAs are more immune
cordic
- we propose a low-cost sequential and high performance architecture for the implementation of CORDIC algorithm in two computation modes. It suited for serial operation that performs conversion between polar and rectangular coordinate systems, essentia
Improving-the-Active-Power-Filter-Performance
- Abstract—In this paper a current reference generation method for a voltage source shunt active power filter is examined. The proposed method improves the harmonic filtering by compensating the delays in the system. In stationary operating poi
cs16
- performance enhanced delay modelled multiplier accumulator
445
- 此程序用于检测EEPROM性能，测试方法如下：写入24c02一个数据，然后在内存中改变这些数据， 掉电后主内存将失去这些信息，然后从24c02中调入这些数据。看是否与写入的相同。这里用8个LED演示 函数是采用软件延时的方法产生SCL脉冲,固对高晶振频率要作 一定的修改....(本例是1us机器 周期,即晶振频率要小于12MHZ)-This procedure is used to detect EEPROM performance, test methods are as
CodeSwitch-
- 本代码为编码开关代码，编码开关也就是数字音响中的 360度旋转的数字音量以及显示器上用的（单键飞梭开 关）等类似鼠标滚轮的手动计数输入设备。 我使用的编码开关为5个引脚的，其中2个引脚为按下 转轮开关（也就相当于鼠标中键）。另外3个引脚用来 检测旋转方向以及旋转步数的检测端。引脚分别为a,b,c b接地a，c分别接到P2.0和P2.1口并分别接两个10K上拉 电阻，并且a，c需要分别对地接一个104的电容，否则 因为编码开关的触点抖动会引起轻微误动作。本程序不
adder128x
- 128位加法器优化设计：64位加法运算+2-1多路选择器。并在关键路径上添加寄存器，降低延迟。 testbench可以测试优化的效果，在ISE中做过综合，能跑到200+MHz-128-bit adder optimization design: 64-bit adder+ 2-1MUX. In the key path, there are regs to improve the performance and reduce the delay time. you use the tes
xy7z.ZIP
- 电动汽车用高效回馈制动控制策略Uncertain singular systems with time-delay H _ guaranteed performance control-Uncertain singular systems with time-delay H _ guaranteed performance control
Fire-Fighting-Robot-An-Approach
- robotic code In On-chip DSM and UDSM VLSI Circuits because of increase device densitities and operating clock frequency the crosstalk noise, crosstalk induced delay, interconnect delay , signal integrity affect the performance and reliabilit
SmartRing
- 本系统结合嵌入式技术、图像处理技术，图像传输技术，Zigbee技术，Web服务器技术设计并实现了一种可靠性高、性能优良、成本低的嵌入式视频门铃系统。该系统使用QT编写，选用S3C6410微处理器作为核心板控制器，采用USB接口的摄像头对来访者进行录像采集，通过嵌入式Web服务器技术实现可靠的远程视频监控，采用GPRS通信技术实现与手机终端的短信通信功能，采用Zigbee技术实现了温室度的采集与无线传输。测试表明，设计的系统视频采集效率高、图像连续性好；远程控制流程延时较小；GPRS通信错误率低，
Dynamic-Noise-Reduction-Algorithm
- n this paper, a new dynamic noise reduction algorithm is proposed based on time-variety filter (TVF), which can be implemented in both time and modified discrete cosine transform (MDCT) domain. In time domain, an IIR filter with changeable ba
key
- 51单片机新型按键扫描，不用10ms延时消抖，实时性大大提高。每个按键有长按短按功能，采用结构体对象化编程，增加按键极度方便。(The new key scan does not use 10ms delay to eliminate jitter, and the real-time performance is greatly improved. Each button has a long press, a short press function, the use of structur