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RC_A7105Reference-code
- A7105 2.4G 160通道无线方案。 这文件系统对RF chip -A7105 FIFO mode做的应用范例程式源码，供使者能够了快速使用这款RF chip。包括跳频技术等，都有详细讲解。-This document describes development of simple example procedures by A7105 FIFO mode. It could support user how to implement two-way radio and how t
FIFO
- 用verilog实现异步FIFO，代码中有两个模块，使用时注意顶层模块和底层模块，用quartus2即可打开直接使用。-Verilog using Asynchronous FIFO, the code has two modules, when the attention of top-level module and the bottom module, with direct access to open quartus2.
fifo的vhdl原代码
- 本文为verilog的源代码-In this paper, the source code for Verilog
Fifo
- 一个FIFO源代码，基于Altera FPGA-A FIFO source code, based on Altera FPGA
FIFO
- it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.-it is a
fifo-interface
- fifo(1-6:1):using ip-code and rd wd interface-fifo:using ip-code and rd wd interface
fifo
- 用VHDL语言写的FIFO代码，可设FIFO的深度-VHDL language with code written in FIFO, FIFO depth can be set up
FIFO
- This code is a FIFO memory vhdl developed in ISE Software
fifo
- fifo 的vhdl源程序,容量为1024*8的fifo程序代码-fifo the vhdl source code,Capacity of 1024* the fifo code 8
fifo.vhd
- This a FIFO in VHDL Code-This is a FIFO in VHDL Code
fifi
- FIFO code written in VHDL
fifo
- 格雷码对地址编码的异步FIFO的实现方法-Gray code encoding to address the realization of the asynchronous FIFO method
FIFO-UART
- 基于ARM7-LM3S1138的FIFO方式的UART数据传输代码-ARM7-LM3S1138 based on the FIFO mode of UART data transmission code
FIFO
- 完整的FIFO完整源代码，通过仿真 完整的FIFO完整源代码，通过仿真 -Complete FIFO full source code, through the simulation of the complete FIFO full source code, through the simulation of
fifo
- 用FPGA做的fifo，源码，调试通过，有工程和波形文件-FPGA to do with the fifo, source code, debugging through, there are engineering and waveform file
fifo
- fifo的代码,经过测试可以使用，很有用处，可以放心使用-a fifo module,the code has been tested and it is usefull
FIFO
- vhdl code for FIFO memory with controler
fifo
- Asynchronous FIFO source code
Asynchronous-FIFO-design
- 异步FIFO是一种先进先出的电路，在异步电路中，由于时钟之间周期和相位完全独立，因而数据丢失概率不为零。如何设计一个高可靠性、高速异步的FIFO是一个难点，本代码介绍了一种解决方法。-Asynchronous FIFO is a kind of advanced first out circuit, in asynchronous circuit, as the clock cycle and phase between full independence, thus data loss pro
FIFO
- FIFO code in verilog