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32chengfa
- 32位乘法，将16位数据和系数扩展32位数，10抽头FIR滤波器-32-bit multiplication, the 16-bit data and coefficient of expansion of 32-digit, 10-tap FIR filter
fir
- 16阶FIR VHDL程序并附带testbench，并有简单流水线设计！-16 Tap FIR vhdl code with testbench and pipelining design
fir_16.txt
- the code performs the fir 16 tap filter operation
fir4tap1
- fir 4 tap code in VHDL
FIR-Filter
- FIR Digital Filters for 4-tap. Its is a general code, change coefficients to design HPF and LPF.
ra3_lib
- serial FIR filter with 2048 tap. Clock runs 4048 times faster than sampling frequency to finish FIR filter calculations before the next sample. Filter coefficients can be loaded in ROM as .hex file. Suitable for room reverberation and high order filt
matlab-and-verilog-fir4_3
- 四抽头FIR滤波器matlab,verilog顶层，子模块，以及testbench代码-Four tap FIR filter matlab, verilog top, sub modules, as well as the testbench code
Low-Power-FIR-Filter
- FIR滤波在数字信号领域中很大作用。这个源码很大帮助VHDL工程师或学习者。里面包含说明书。-This report investigates the power consumption of digital arithmetic circuits for use in the design and implementation of a 15-tap programmable Finite Impulse Response (FIR) filter.
fir4tap using array
- 4 tap fir filter using by passing multiplier
8
- filter fir tap implementation
滤波器实验报告
- 设计一个 1MHz 的 FIR 低通滤波器。 要求： ① 时钟信号频率 16MHz; ② 输入信号位宽 8bits，符号速率 16MHz ③ 要求在 Matlab 软件中进行 FIR 滤波器浮点和定点仿真，并确定 FIR 滤波器抽头系数 ④ 写出测试仿真程序。(Design a 1MHz FIR low pass filter. Requirements: (1) clock signal frequency 16MHz; (2) input signal bit width
哈夫曼编码器设计实验报告
- 要求对一段数据序列进行哈夫曼编码，使得平均码长最短，输出各元素编码和编码后的数据序列。 ①组成序列的元素是[0-9]这10个数字，每个数字其对应的4位二进制数表示。比如5对应0101，9对应1001。 ②输入数据序列的长度为256。 ③先输出每个元素的编码，然后输出数据序列对应的哈夫曼编码序列。(Design a 1MHz FIR low pass filter. Huffman coding is required for a section of data sequence to m