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浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算,结合vhdl和EPGA可编程技术,完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmab
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floating point adder mul and sub in verilog code
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the code describle a floating point adder with verilog
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verilog implementation of the floating point adder
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浮点加法器的用Verilog实现,32位的浮点加法器-Floating point adder Verilog
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一个浮点加法器,verilog描述,数据格式:高14位为尾数,低四位位指数(带符号数运算)-A floating point adder Verilog descr iption
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基于Verilog HDL的32位浮点运算加法器的源代码。-Based on the 32-bit floating point adder in Verilog HDL source code.
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32位浮点加法器
verilog语言编写-32-bit floating-point adder verilog language
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该源码利用Verilog HDL语言成功实现了浮点数的加法运算,包括全部工程以及Verilog 源码,经验证,该程序成功实现了浮点数的加法。-The use of Verilog HDL source language of the successful implementation of floating-point addition operation, including all engineering and Verilog source code, proven, successful
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能够实现单精度浮点加法运算。输入引脚有:第一运算数,第二运算数,复位信号,时钟信号。输出信号有:运算结果,运算完成标志。(To achieve a single precision floating-point addition operations)
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32 bit floating point adder with testbench
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