搜索资源列表
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2下载：
32位浮点乘法器的源代码，用verilog来实现的-32-bit floating point multiplier source code to achieve with verilog
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新型的浮点乘法器 用csa来实现可以用在浮点乘法器的地方-A new type of floating-point multiplier with CSA to achieve floating-point multiplier can be used in place
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Simple 32 bit Floating point Multiplier
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Floating point multiplier
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Floating Point Multiplier in VHDL
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用Verilog实现一位原码浮点数乘法器，按照累加的方式，逐位相乘，再相加。-Verilog realization of an original code with floating point multiplier, in accordance with the cumulative way, bit by bit multiply, then add.
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CF Floating Point Multiplier
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verilog implementation of the floating point multiplier
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this file is the vhdl codes for floating point multiplier.
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this file is vhdl codes for rounding the floating point number to nearest number.it is useful for floating point multiplier.
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the document used to describe the verilog codes design floating point multiplier in coms design
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Floating Point Multiplier in Verilog
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floating point multiplier unit developed in vhdl
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Implementation of 32-bits Floating Point Multiplier, based on IEEE 754 Standard
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单精度浮点数乘法器，用组合逻辑资源实现，-Single-precision floating-point multiplier, using a combination of logic resources
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Verilog语言编写的单精度浮点数乘法器-The Verilog language of single precision floating point multiplier
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浮点数 乘法器带绝对值运算 verilog语言编写 可直接调用-Floating-point multiplier verilog language with absolute operation can be called directly
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floating point multiplier in VHDL
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An FPGA Based High Speed IEEE-754 Double Precision Floating Point Multiplier
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verilog code for floating point multiplier
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