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uart frame det
- 自己的小作,能简化繁琐的通讯帧格式的检测工作,在常量数组 PROTOCOL_ARRAY 中定义一个或多个通讯帧格式,能同时将多个有效帧检测出来,采样队列的方式,高效.-for their small, can simplify the cumbersome communications frame format detection, the constants defined array PROTOCOL_ARRAY one or more communications frame format
TFTDriverNew_V2
- TFT液晶屏驱动模块Verilog源码。实现方法：XC95288+K6R4008，K6R4008主要用作帧缓冲区，此模块仅支持256色-TFT LCD driver module Verilog source code. Realization: XC95288+ K6R4008, K6R4008 mainly used as a frame buffer, this module only supports 256 colors
MR7910
- 数位相框厂牌MARS主力IC-MR7910的FIRMWARE,SCH,DRIVER,SETUP,UNV文件，吐血奉献！-MARS Digital Photo Frame manufacturer of IC-MR7910 main FIRMWARE, SCH, DRIVER, SETUP, UNV paper, hematemesis dedication!
photo-frame
- 一篇用FPGA做数字相框的论文.有实际制作指南.-a paper on Digital photo frame with a FPGA.
Digital-Photo-Frame
- 基于QT编译的数码相框程序，可以自动播放相片，有翻页特效。-QT-based digital photo frame compiled program that can automatically play photo, there are flip effects.
cameralink
- 由于目前基于CameraLink接口的各种相机都不能直接显示，因此本文基于Xilinx公司的Spartan 3系列FPGAXC3S1000-6FG456I设计了一套实时显示系统，该系统可以在不通过系统机的情况下，完成对相机CameraLink信号的接收、缓存、读取并显示 系统采用两片SDRAM作为帧缓存，将输入的CameraLink信号转换成帧频为75Hz，分辨率为1 024×768的XGA格式信号，并采用ADV7123JST芯片实现数模转换，将芯片输出的信号送到VGA接口，通过VGA显示器显示
SDH
- SDH开销的接收处理，要求： 1， A1和A2字节为帧头指示字节，A1为“11110110”，A2为“00101000”，连续3个A1字节后跟连续3个A2字节表示SDH一帧的开始。要求自行设计状态机，从连续传输的SDH字节流中找出帧头。 2， E2字节为勤务话通道开销，用于公务联络语音通道，其比特串行速率为64KHz(8*8K=64)。要求从SDH字节流中，提取E2字节，并按照64K速率分别串行输出E2码流及时钟，其中64K时钟要求基本均匀。（输出端口包括串行数据和64K串行时钟）
HDLC
- hdlc帧接收器 包含文件： 设计代码 测试代码 综合脚步 说明文档-HDLC frame receiver include file: design code test code Comprehensive documentation footsteps
SDH_module
- SDH帧同步头的检测，并提取其中的语音信息的模块设计-SDH frame sync detection, and extract audio information module design
Digita_Photo_Frame
- avr+TFT+SD卡实现数码相框功能-avr+ TFT+ SD Card Digital Photo Frame Function
SPI_TEST
- The Serial Peripheral Interface Bus or SPI bus is a synchronous serial data link standard named by Motorola that operates in full duplex mode. Devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave d
m03b
- MSTAR03的数码相框的代码，可做读卡器，支持CARD，USB，个性化的界面哦，已经量产的-Digital Photo Frame MSTAR03 of the code reader can do in support of CARD, USB, personalized interface Oh, already in volume production of
AIC
- 使用FPGA/CPLD设置语音AD、DA转换芯片AIC23，FPGA/CPLD系统时钟为24.576MHz 1、AIC系统时钟为12.288MHz，SPI时钟为6.144MHz 2、AIC处于主控模式 3、input bit length 16bit output bit length 16bit MSB first 4、帧同步在96KHz-The use of FPGA/CPLD set voice AD, DA conversion chip AIC23, FPGA/
Flashcontrollerxilinx
- Single power supply operation — Full voltage range: 2.7 to 3.6 volt read, erase, and program operations — Separate VCCQ for 5 volt I/O tolerance n Automated Program and Erase — Page program: 512 + 16 bytes — Block erase: 8 K + 256 bytes
uart_0910
- uart串口传输的verilog RTL级源码，已通过仿真验证。文件主要包含发送、接受位处理，发送、接受字节帧处理，对学习串口通信的朋友很有帮助-uart serial transmission verilog RTL-level source code has been verified by simulation. File mainly contains the send, receive digital processing, sending, receiving bytes of fr
rzn725SDH
- 一个关于SDH中TU-12解帧的VHDL代码-On the SDH in a solution of TU-12 frame VHDL code for
motion
- This project deals with the tracking and following of single object in a sequence of frames and the velocity of the object is determined. Algorithms are developed for improving the image quality, segmentation, feature extraction and for deterring
E1
- 在国际标准组织开放式系统互联（OSI）参考模型下，以太网是第二层协议。10G以太网使用ＩＥＥＥ（电气与电子工程师学会）802.3以太网介质访问控制协议（ＭＡＣ）、ＩＥＥＥ 802.3以太网帧格式以及ＩＥＥＥ 802.3最小和最大帧尺寸。-In the International Standards Organization Open Systems Interconnect (OSI) reference model, Ethernet is the second-layer protocol.
Frame-synchronization
- FPGA 帧同步源代码 调试无错误 ALTERA 平台-Frame synchronization FPGA
Digital-photo-frame
- 在linux下用QT开发的一个数码相框程序，包含背景音乐播放、图片手动浏览、图片自动浏览等功能。经过交叉编译以后，可以在移植有包含Qtopia-2.2.0的文件系统上运行。程序中使用的文件类为自己编写。-QT under linux with the development of a digital photo frame program, including background music, pictures, manual browsing, automatic picture viewe